Sequential Function Charts (SFCs)

• Sequential Function Charts (SFCs) are a graphical formalism standardized in IEC 61131-3 that defines sequential control logic using steps, transitions, and actions.
• They enable formal verification and automated synthesis by leveraging process algebra, Petri Net theory, and invariant-based proofs.
• SFCs support interoperability between graphical and textual representations, facilitating reliable transformation into executable code for mixed hardware/software systems.

Sequential Function Charts (SFCs) are a graphical formalism standardized in IEC 61131-3 for modeling the sequential control logic of industrial automation systems, particularly those governed by Programmable Logic Controllers (PLCs). SFCs occupy a critical role at the top-level specification, enabling modular, state-based definition of processes, their sequencing, and synchronization through steps (states), transitions (guards), and actions (code blocks). Modern SFC engineering encompasses their formal treatment via process algebra, Petri Net theory, semantics encoding for verification, and automated synthesis for deployment in both software (e.g., microcontrollers) and hardware (e.g., programmable logic devices) (Blech et al., 2013, Glick et al., 7 Dec 2025, Ferreira et al., 2011, Blech et al., 2010, Blech, 2011).

1. Formal Syntax and Graph-Theoretic Structure

SFCs describe control logic as a directed graph whose vertices are steps and whose edges are transitions. Formally, an SFC is modeled as a tuple $(S, S_0, T, A, F, V, Val)$ where:

• $S$: set of step identifiers;
• $S_0 \subseteq S$: set of initially active steps;
• $T$: set of transitions, each a triple $(S_{in}, \text{guard}, S_{out})$;
• $A$: set of action blocks;
• $F$: mapping from steps to lists of action blocks, $F: S \rightarrow \text{list}(A)$;
• $V$: set of variables;
• $Val$: types of variable values (e.g., integers, booleans).

Each transition defines its source steps, the Boolean guard condition on system memory, and the target steps to activate when the guard is true and all source steps are active (Blech et al., 2013, Blech, 2011). Graph-theoretic underpinnings relate SFCs to restricted Petri Nets (Grafcet) where steps correspond to places, transitions to bars, and the flow relation $F$ connects places and transitions (Ferreira et al., 2011).

2. Operational Semantics

The operational semantics of an SFC are defined in terms of system states $(m, S_\text{active}, A_\text{pending})$, where $m: V \rightarrow Val$ is the global memory, $S_\text{active} \subseteq S$ the currently active steps, and $A_\text{pending} \subseteq A$ the set of actions pending execution. Execution is defined via:

• Action execution: selecting and applying an enabled action block $a \in A_\text{pending}$, updating $m$ and removing $a$ from $A_\text{pending}$.
• Step transition: firing a transition whose source steps are all active and whose guard evaluates to true, provided all actions of source steps have completed; this deactivates the source steps and activates the target steps, scheduling their actions (Blech et al., 2013, Blech et al., 2010, Blech, 2011, Ferreira et al., 2011).

Formally, these transitions are inductively defined, enabling systematic proof construction: $$\begin{aligned} &(\text{ExecAction}) \quad (m, A \cup\{a\}, S) \longrightarrow_1 (m', A \setminus \{a\}, S) \ &(\text{Step}) \quad (m, S, A) \longrightarrow_1 (m, (S \setminus S_{in}) \cup S_{out}, A \cup \bigcup_{s \in S_{out}} F(s)) \end{aligned}$$ (Blech et al., 2013, Blech, 2011).

3. Tooling and Automated SFC Synthesis

Tool chains for SFC engineering support graphical or textual specification, formal validation, and code generation. Key frameworks include:

• CERTPLC: Accepts graphical SFCs (e.g., from EasyLab), generates Coq representations encoding syntax and semantics, and produces proof scripts certifying properties by inductive invariant reasoning. CERTPLC guarantees model consistency and enables independently checkable machine-verifiable certificates for safety and liveness (Blech, 2011, Blech et al., 2013).
• ISaGRAPH-based toolchain: Allows round-tripping between graphical (IEC 1131–3 compliant) and textual representations, validates conflict/liveness properties, then synthesizes C code for microcontroller deployment or Palasm netlists for PLDs. This enables mixed HW/SW implementations where slow supervisory logic executes in software and fast loops in dedicated hardware (Ferreira et al., 2011).
• LLM4SFC: Uses retrieval-augmented, grammar-constrained LLMs to generate syntactically valid SFC programs from natural language workflow descriptions, targeting both reduced representations and vendor-neutral PLCopen XML output. Pass rates for syntactic and semantic validation reach 75%–94% depending on model type (Glick et al., 7 Dec 2025).

4. Invariant-Based Formal Verification

Safety and correctness properties of SFC-modeled systems are proven by inductive invariants over reachable states. In Coq, reachability is an inductive predicate:

Inductive reachable : State → Prop := | r_init : reachable (m₀, [], S₀) | r_step : ∀ c c′, reachable c → (executeAction c c′ ∨ stepTransition c c′ ) → reachable c′.

To certify a property $P(s)$, two obligations are discharged:

1. $P$ holds in the initial state,
2. For each transition $s \rightarrow_1 s'$, $P(s)$ implies $P(s')$ (Blech et al., 2013, Blech, 2011). Tactics automate arithmetic solvers, case distinctions, and contradiction elimination when reasoning about transitions and guards. Sample properties (e.g., mutual exclusion, reachability of distinguished steps) are common, and model checkers (NuXmv, PLCreX) validate syntactic and safety aspects for generated charts (Glick et al., 7 Dec 2025).

5. Interoperability and Transformation

SFC models are often automatically transformed into other formal frameworks:

• C code and Palasm netlists: For direct deployment on microcontrollers or PLDs, ensuring equivalence with the validated high-level control logic (Ferreira et al., 2011).
• BIP transformation: SFCs are systematically mapped to BIP atomic components, gluing step and action semantics via connectors to preserve behavioral and invariant properties under transformation. Each SFC artifact (steps, actions, transition guards, global variables, manager) becomes a BIP component, enabling property lifting and tool-supported invariant checking (Blech et al., 2010).

6. Application Domains and Representative Examples

Engineers in industrial automation utilize SFCs for applications such as sorting stations, conveyor sequences, and load/unload controllers. Real-world SFC datasets (e.g., 2,390 charts over 34 industrial projects) support both validation and parameterization of generative or verification models (Glick et al., 7 Dec 2025). Representative workflows, such as a sorting demonstrator featuring sensor-driven branching, actuator scheduling, and mutual exclusion of alternatives, are encoded into both formal Coq definitions and executable logic. The modularity and diagrammatic clarity of SFCs facilitate formal reasoning and practical synthesis in automated manufacturing environments (Blech et al., 2013, Ferreira et al., 2011).

7. Challenges, Limitations, and Future Directions

Ongoing difficulties in SFC practice include the gap between graphical and textual representations (especially in verbose PLCopen XML), embedded code generation and integration (notably Structured Text actions), scarcity of public corpora for learning-based synthesis, and enforcing semantic safety (excluding illegal jumps or unsynchronized merges). Current conflict-resolution is basic, with more advanced Petri Net-based analyses planned (Ferreira et al., 2011), and fine-grained step interruption still introduces hazards. Emerging research targets multimodal models, improved verification loops, and open-source corpora, aiming for fully automated, correct-by-construction PLC logic generation (Glick et al., 7 Dec 2025).

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References:

• (Blech et al., 2013) On Formal Reasoning on the Semantics of PLC using Coq
• (Glick et al., 7 Dec 2025) LLM4SFC: Sequential Function Chart Generation via LLMs
• (Ferreira et al., 2011) Automatic Generation of C-code or PLD Circuits under SFC Graphical Environment
• (Blech et al., 2010) Towards a Property Preserving Transformation from IEC 61131-3 to BIP
• (Blech, 2011) A Tool for the Certification of PLCs based on a Coq Semantics for Sequential Function Charts