SAT-MapIt: SAT-Based Mapping & Scheduling

• SAT-MapIt is a methodology that encodes complex mapping and scheduling problems into CNF formulas, enabling global optimality in resource-constrained systems.
• It employs key techniques like Kernel Mobility Schedule, exactly-one assignment, and dependency routing to ensure optimal placement and pipelining in CGRA and quantum circuits.
• Experimental results show that SAT-MapIt outperforms heuristics by reducing initiation intervals and improving register allocation, achieving significant speedups in challenging benchmarks.

SAT-MapIt refers to a class of methodologies and toolchains that leverage Boolean satisfiability (SAT) solvers to optimally solve various computational mapping problems. Its principal applications are in hardware-loop mapping for coarse-grained reconfigurable architectures (CGRA), resource-constrained accelerator scheduling, quantum circuit SWAP-insertion, and, more generally, in combinatorial optimization scenarios where traditional graph-based or heuristic techniques do not guarantee global optimality. SAT-MapIt systems encode key placement, routing, scheduling, and resource constraints as conjunctive normal form (CNF) Boolean formulas, allowing the use of modern SAT solvers to exhaustively explore the solution space.

1. Boolean SAT Formulation for Resource Mapping

SAT-MapIt for CGRA mapping reframes loop scheduling as a pure SAT problem. The computation kernel (typically represented by a Data-Flow Graph—DFG) is mapped to the underlying hardware's mesh of Processing Elements (PEs). Each mapping instance introduces Boolean variables $x_{i,p,c,it}$, indicating node $i$ in iteration $it$ is assigned to PE $p$ at cycle $c$ (Tirelli et al., 2 Dec 2025, Tirelli et al., 2 Dec 2025, Tirelli et al., 20 Feb 2024). Three constraint classes form the CNF:

• Exactly-one assignment: Each operation appears once per kernel window:

$$\bigvee_{x \in \mathcal{L}(i,it)} x\quad \text{and}\quad \forall x \neq y \in \mathcal{L}(i,it),\;\neg(x \wedge y).$$

• Resource exclusivity: No two nodes share a PE, cycle, and iteration:

$\forall p,c,it\quad \sum_{i}x_{i,p,c,it} \leq 1.$

• Dependency and routing: For every DFG edge, node placements and instance timings must satisfy architectural adjacency, latency, and iteration-distance constraints (via explicit or implicit neighborhood pairing and scheduling modulo II).

This encoding achieves a fully unified search over temporal, spatial, and resource dimensions, allowing the SAT solver to coordinate placements and pipelining optimally.

2. Kernel Mobility Schedule: Formal Definition and Significance

A central innovation is the Kernel Mobility Schedule (KMS), which expresses all legal placements and timings for DFG nodes under modulo scheduling. KMS is constructed by:

• Computing ASAP (as-soon-as-possible) and ALAP (as-late-as-possible) times for each node for a candidate Initiation Interval (II).
• Folding the standard mobility windows modulo II over enough overlapping iterations to cover all dependency heights.
• Enumerating all $(i,c,it)$ combinations such that $c = t \bmod \mathrm{II}$, $it = \lfloor t / II\rfloor$, with $t$ within the node’s mobility range $[e_i, \ell_i]$.

Thus, each SAT variable $x_{i,p,c,it}$ is only introduced if the bundle $(i,p,c,it)$ is permitted by the KMS (Tirelli et al., 2 Dec 2025, Tirelli et al., 2 Dec 2025, Tirelli et al., 20 Feb 2024). KMS defines the "universe" of feasible mappings and compresses the temporal dimension for overlapping loop iterations.

3. Iterative Solution and Register Allocation

SAT-MapIt solves for the minimum II via iterative deepening:

• Initialize II to the resource or recurrence lower bound, e.g., $\lceil|\text{DFG}|/|\text{PEs}|\rceil$ or by loop-carried dependency length.
• For each II, generate KMS, allocate variables, and emit all CNF constraints.
• Invoke the SAT solver; if unsatisfiable, increment II and repeat.
• Upon SAT, extract assignments and perform register allocation per PE (coloring interference graphs of live edges for register files, typically four per PE).
• If register allocation fails, increment II and continue (Tirelli et al., 2 Dec 2025, Tirelli et al., 20 Feb 2024, Tirelli et al., 2 Dec 2025).

This procedure guarantees minimal II within practical timeout limits. In experimental studies across benchmarks and CGRA sizes, SAT-MapIt found strictly lower II than state-of-the-art (SoA) heuristic tools in 47.72%–82% of cases and discovered valid mappings where existing methods could not.

4. Application to Quantum Circuit SWAP Mapping

SAT-MapIt extends naturally to initial placement for SWAP gate strategies in quantum circuits with commuting gates—critical for sparse connectivity quantum hardware (Matsuo et al., 2022). Here, the mapping problem is reduced to finding an injective matching $x_{i,v}$ between logical qubits $i$ and physical qubits $v$ such that the program graph embeds into the effective hardware graph after $l$ SWAP layers. Key SAT constraints enforce injectivity and adjacency:

• One-to-one mapping/injectivity:

$$\forall i\ \bigvee_{v} x_{i,v} = 1;\quad \forall v \forall i\neq j\ \neg(x_{i,v} \wedge x_{j,v}) = 1.$$

• Edge-preservation: For each program edge $(i,j)$ and hardware edge $(v,w)$ in $C_l$,

$\neg x_{i,v} \vee \bigvee_{(v,w) \in E_l} x_{j,w}.$

• Binary search over $l$ determines the minimum number of SWAP layers required.

A clustering heuristic divides large $n$-node graphs into clusters, solving smaller SAT instances sequentially to break the $O(n^2)$ variable bottleneck, at the cost of slight optimality loss but with scalability to $n \approx 1000$ (Matsuo et al., 2022).

5. Experimental Results and Performance

Comprehensive benchmarking demonstrates the efficacy of SAT-MapIt:

Benchmark/Domain	Lower II found (%)	SoA mapping found	Speedup in hard cases
CGRA (MiBench/Rodinia)	47.72–82	RAMP, PathSeeker	$\sim$962 s faster
Quantum SWAP Mapping	Up to –76% layers	SABRE, random	O(log n) SAT calls

SAT-MapIt consistently achieves or matches the theoretical minimum II, enables mappings on resource-constrained meshes (2×2), and outperforms graph-based or heuristic approaches especially on difficult, highly-constrained problems (Tirelli et al., 2 Dec 2025, Tirelli et al., 20 Feb 2024, Tirelli et al., 2 Dec 2025, Matsuo et al., 2022).

6. Scalability, Limitations, and Extensions

The primary scaling challenge is the superlinear growth in SAT variables and clauses with mesh size, DFG complexity, and II candidate. SAT-MapIt leverages cardinality encodings, clause learning, symmetry breaking, and pruning, and supports mesh sizes up to 5×5 and DFGs of several dozen nodes. Limitations include:

• Implicit routing—current models do not encode multi-hop routing explicitly, sometimes missing the absolute optimal II.
• Register allocation is post-hoc; tighter SAT–register integration is a natural enhancement.
• Sequential II increment; binary or heuristic interval search would accelerate convergence.
• Clustering for large-scale quantum mapping breaks global optimality (Tirelli et al., 2 Dec 2025, Tirelli et al., 20 Feb 2024, Matsuo et al., 2022).

Potential extensions include full multi-hop routing SAT modeling, tighter register pressure integration, incremental SAT encoding, and SAT-guided architecture exploration (Tirelli et al., 20 Feb 2024).

7. Contextual Integration: SAT-MapIt's Place in Solver Technologies

SAT-MapIt exemplifies a broader principle: the translation of intricate hardware/software mapping and scheduling problems into satisfiability domains, leveraging advances in CDCL and SMT solving paradigms (Tirelli et al., 2 Dec 2025, Tirelli et al., 20 Feb 2024). Its modular SAT encoding integrates dataflow, architectural, and temporal properties into a single global search. In quantum and classical hardware, this enables scalable, optimal, and verifiable mapping, outperforming localized, instance-specific heuristics.

A plausible implication is that further refinement and interoperability (e.g., incremental SAT, abstraction refinement, hardware/software code-generation feedback loops) will extend SAT-MapIt’s reach to even larger systems, heterogeneous architectures, and dynamic real-time scheduling scenarios.