SAGE-HLS: AST-Guided HLS Code Generation

• SAGE-HLS is a syntax-aware, AST-guided LLM tailored for generating high-level synthesis (HLS) code from C/C++ hardware descriptions.
• It leverages a novel, semi-synthetic 16.7k-example HLS-C/C++ corpus with explicit syntax supervision to overcome dataset scarcity and improve structural generalization.
• Experimental results demonstrate near-perfect synthesizability and enhanced functional correctness, marking significant progress in automated hardware design.

SAGE-HLS is a syntax-aware, AST-guided LLM specifically developed for high-level synthesis (HLS) code generation. Targeting the challenges of synthesizing hardware from C/C++ descriptions, SAGE-HLS leverages program structural information and a novel dataset construction pipeline to address core bottlenecks in automated hardware design, such as dataset scarcity, poor structural generalization, and lack of standardized evaluation. Fine-tuned on QwenCoder 2.5–7B using a 16.7k-example HLS-C/C++ corpus with explicit syntax supervision, SAGE-HLS achieves near-perfect synthesizability and improved functional correctness, advancing the capabilities of LLMs in the electronic design automation (EDA) domain (Khan et al., 5 Aug 2025).

1. Motivation and High-Level Synthesis Landscape

High-level synthesis transforms behavioral descriptions in C or C++ to synthesizable register-transfer level (RTL) hardware representations suitable for FPGA and ASIC flows. While HLS promises accelerated hardware development, the productivity gains are counterbalanced by the expertise required for optimal power, performance, and area (PPA) results—typically achieved through explicit pragma insertion, loop optimizations, and memory partitioning.

Traditional LLMs (e.g., Codex, CodeGen, QwenCoder) have demonstrated strong results in general code generation. However, their utility for HLS design automation has been constrained for two reasons: (1) the absence of large, publicly verified HLS-C/C++ training datasets, and (2) insufficient model awareness of structural program properties—such as control/data flow—which are critical for effective synthesis and optimization. Methods before SAGE-HLS, including HLSPilot, C2HLSC, and SynthAI, have predominantly concentrated on pragma recommendation or relied on prompt engineering and retrieval-augmented generation (RAG), lacking true fine-tuning or deep structural grounding. This has resulted in limited functional correctness and ill-defined evaluation protocols (Khan et al., 5 Aug 2025).

2. Dataset Construction via Verilog-to-HLS-C/C++ Porting

To overcome the dataset bottleneck, SAGE-HLS introduces a semi-synthetic HLS corpus by automating the porting of verified, synthesizable Verilog modules to HLS-compliant C/C++. By collecting approximately 19k Verilog modules from open-source platforms—spanning applications from basic digital filters to cryptographic cores and systolic arrays—and employing GPT-4-guided system prompts, each Verilog design was converted to:

• A functionally equivalent HLS-C/C++ implementation, annotated with #pragma HLS directives under the canonical top_module naming.
• A standalone, natural language instruction enabling LLM-based HLS-C regeneration from specification.

Each HLS-C/C++ output was validated using AMD Vitis HLS for synthesizability. Designs failing to synthesize or exhibiting gross inefficiency were omitted, yielding a high-quality final set of 16.7k HLS-C/C++ examples. Preprocessing steps normalized code style, headers, pragma syntax, and ensured platform-agnosticity (free of board-specific I/O bindings) (Khan et al., 5 Aug 2025).

3. AST-Guided Instruction Prompting and Fine-Tuning Approach

A distinctive feature of SAGE-HLS is its use of abstract syntax trees (ASTs) to represent program structure for both training and inference.

AST Extraction and Processing:

• Each HLS-C example is parsed using Tree-sitter to construct a typed AST.
• The AST undergoes pruning and optimization, collapsing redundant single-child nodes and removing uninformative elements as detailed in Algorithm 1 of the paper.
• A control-flow graph (CFG), capturing loop nests, conditionals, and function calls, is derived from the pruned AST.

Fine-Tuning Schema:

• Each training input comprises: (1) the natural language instruction, (2) a serialized AST representation (e.g., “FuncName: top_module; Params: ap_uint<11>, ...; IfStmt→..., Asgnmt→...”), and (3) the target HLS-C/C++ code.
• The underlying model is QwenCoder 2.5–7B, an open-source transformer-based code LLM.
• Two key variants are developed:
  • QWEN-HLS: fine-tuned on (instruction + plain-text HLS-C)
  • SAGE-HLS: fine-tuned on (instruction + AST + HLS-C)
• Both use LoRA with 4-bit quantization for memory efficiency.

Loss Function:

Training optimizes a compound objective:

$$L_{\text{total}} = L_{\text{NLL}} + \lambda \cdot L_{\text{AST}}$$

where

$$L_{\text{NLL}} = -\sum_{t=1}^{T} \log P_{\theta}(y_t | x_{<t}), \qquad L_{\text{AST}} = -\sum_{e \in \text{Edges(AST)}} \log P_{\theta}(e \,|\, \text{context})$$

with $\lambda \approx 0.1$ balancing standard sequence modeling and AST-consistency (Khan et al., 5 Aug 2025).

4. Evaluation Methodology: VerilogEval Adaptation

SAGE-HLS implements a semi-automated evaluation strategy by adapting the VerilogEval benchmark pipeline—originally designed for RTL generation evaluation—to the HLS context:

• Each task-specific RTL-level instruction is repurposed as an HLS-C/C++ generation prompt.
• Constrained testbenches are automatically generated using GPT-4, producing deterministic stimuli and assertions, following principles from constrained random verification.
• The generated HLS-C code is passed through Vitis HLS to verify synthesizability (generation of a valid RTL netlist).
• Final designs are simulated against the synthesized RTL and the testbench to assess functional correctness.

Evaluation Metrics:

• Synth@k: percentage of generated designs, over k LLM samples, that synthesize successfully.
• Pass@k: percentage that pass all functional assertions.

Near-100% Synth@1 and ≥ 75% Pass@10 are set as strong performance targets for HLS-C generators in this context (Khan et al., 5 Aug 2025).

5. Experimental Results and Model Performance

The core experimental results are summarized below:

Model	Synth@1	Synth@5	Synth@10	Pass@1	Pass@5	Pass@10
QWEN Base (pre-trained)	52.6%	61.5%	70.5%	22.4%	38.5%	43.6%
QWEN-HLS (text-only)	94.9%	98.7%	100%	56.4%	67.9%	71.8%
SAGE-HLS (AST-guided)	93.0%	100%	100%	57.7%	70.5%	75.6%

Both fine-tuned variants achieve near-perfect synthesizability, representing a ≈40 percentage point improvement over the base model. SAGE-HLS provides ≈4 percentage point improvement in Pass@10 over QWEN-HLS, highlighting the benefit of AST guidance—especially for resolving complex control/data-flow bugs.

Performance is stratified by input complexity: for T3 (hard) tasks, SAGE-HLS achieves Pass@1 ≈ 40%, QWEN-HLS ≈ 37%, and the base model less than 10%. On Pass@10, SAGE-HLS reaches ≈68% on the most difficult tier. End-to-end PPA metrics such as area and latency are not reported, with the focus instead on correctness and synthesizability. The embedding of syntactic structure encourages appropriate usage of pipelining and unrolling pragmas, suggesting possible future latency improvements (Khan et al., 5 Aug 2025).

6. Limitations and Future Directions

Principal limitations of SAGE-HLS include the absence of board- or timing-specific pragmas, coverage restricted to generic algorithm kernels, and the use of a linearized AST encoding. As such, PPA trade-offs and cost-aware design automation remain unexplored.

Future directions indicated involve:

• Expanding the dataset to include real-world IPs with vendor-specific directives.
• Joint prediction of resource estimates in parallel with code generation, facilitating intelligent selection of cost-aware pragmas.
• Enrichment of structural representation via advanced graph neural network embeddings incorporating data-flow and memory-access features alongside ASTs.

A plausible implication is that such enhancements may further improve generalization and code quality in complex HLS scenarios (Khan et al., 5 Aug 2025).