Ring Router Microarchitecture

• Ring router microarchitecture is defined as a NoC design that structures internal switching using a circular, bidirectional ring of exchange blocks, eliminating traditional crossbars.
• Experimental results demonstrate a 53% reduction in end-to-end latency along with significant area and power savings under low injection rates.
• The design replaces complex switch allocators with localized multiplexers and distributed arbitration, offering scalable and efficient routing for five-port mesh networks.

A ring router microarchitecture is a Network-on-Chip (NoC) router design in which each router is internally structured as a small bidirectional ring of exchanges, replacing the conventional crossbar-based router architecture. In this approach, each five-port mesh router—typified by the standard North, East, South, West, and Core port configuration—implements its switching and buffering functions by connecting five identical exchange blocks in a circular, bidirectional topology. The ring structure enables the elimination of the traditional 5×5 crossbar and its associated switch allocator, aiming for significant reductions in latency, area, and power compared to baseline router designs. Experimental results demonstrate end-to-end latency reductions of 53%, area reductions of 34%, and power reductions of 27% relative to conventional NoC router implementations synthesized at the 45 nm technology node (Wu, 2020).

1. Ring Topology and Router Structure

The defining feature of the ring router microarchitecture is its treatment of the router’s internal datapath as a small, bidirectional ring network, composed of five “exchanges” (XCs). Each exchange connects to exactly one external port (either North, East, South, West, or Core) and two neighboring exchanges in the ring. Clockwise and counter-clockwise logical rings provide two internal dataflow paths. A single logical disjoint, implemented at the Core exchange, creates a break in one of the virtual channel rings to prevent deadlock.

The canonical internal topology is shown below (ASCII representation):

$$d_{\text{exch}} = 1\ \text{cycle},\quad d_{\text{link}} = 1\ \text{cycle}$$1

Within each exchange:

• Three unidirectional input ports and three output ports are each equipped with a banked FIFO buffer array (three banks per exchange, two virtual channels per bank in the evaluated design).
• The exchange comprises a Route Computation Unit (RCU) to process the destination coordinates and forward the flit to the correct next-ring neighbor, a Buffer Arbiter (BA) to select among incoming ring directions, and an Output Arbiter (OA) to select the releasing virtual channel.
• The conventional router’s crossbar and switch allocator are replaced by per-buffer 2:1 multiplexers and localized arbiters.

2. Data Flow and Control Mechanisms

A flit entering one exchange traverses it in exactly one cycle, participating in a micro-pipeline as follows:

1. Incoming flits arrive at a ring-direction input, its lookahead routing tag set in the prior exchange.
2. During the same cycle, the BA arbitrates (round-robin) between the two ring-direction ports competing to write into a buffer.
3. The OA selects among up to two virtual channels in a buffer for transmission downstream.
4. Because internal buffers are dual-ported, read and write can occur simultaneously, ensuring one cycle per exchange traversal.

The ring router employs strict credit-based flow control with eight flits per VC FIFO. Arbitration within each exchange is conducted in a round-robin fashion for both the BA and OA, guaranteeing fair and starvation-free access:

$$\text{grant}_{i} = \begin{cases} 1 & \text{if request}_{i} = 1 \;\wedge\; (\text{last\_grant}+1) \bmod 2 = i \ 0 & \text{otherwise} \end{cases}$$

3. Performance Analysis

3.1 Latency Modeling

Under ideal (no-contention) conditions, each hop through a router consists of one exchange cycle and one inter-router link cycle:

$$d_{\text{exch}} = 1\ \text{cycle},\quad d_{\text{link}} = 1\ \text{cycle}$$

If a packet traverses $H$ routers:

• Ring router latency:

$$\text{Latency}_{\text{ring}} = H(d_{\text{exch}} + d_{\text{link}}) = 2H\ \text{cycles}$$

• Conventional router latency:

$$\text{Latency}_{\text{conv}} \approx H(4 + d_{\text{link}}) \approx 5H\ \text{cycles}$$

3.2 Empirical Results

On an 8×8 mesh, simulating one-flit packets under various synthetic traffic patterns, the ring router achieves on average:

• 53% lower end-to-end latency at low injection rates (i.e., 0.47× versus baseline)
• Comparable or slightly later network saturation point

4. Area and Power Evaluation

4.1 Synthesis Process

Both conventional and ring routers were described in Verilog and synthesized for a 45 nm process using Cadence EDA tools. Area and power results are reported based on post-synthesis netlists including placement and routing estimates.

4.2 Area/Power Comparison

The equations for area cost are:

• Conventional:

$$A_{\text{conv}} = N_{\text{VC,conv}} \times A_{\text{cell}} + A_{\text{Xbar}} + A_{\text{alloc}}$$

• Ring:

$$A_{\text{ring}} = N_{\text{VC,ring}} \times A_{\text{cell}} + N_{\text{mux2:1}} \times A_{\text{mux}} + A_{\text{arb}}$$

Where:

• $N_{\text{VC,conv}} = 5 \times 8 = 40$
• $N_{\text{VC,ring}} = 5 \times 3 \times 2 = 30$

Synthesized results indicate:

• Area reduction: $34\%$
• Power reduction: $$d_{\text{exch}} = 1\ \text{cycle},\quad d_{\text{link}} = 1\ \text{cycle}$$0

5. Comparative Results

The following table summarizes normalized performance metrics versus two baseline designs (“base-1”: conventional, “base-2”: conventional with lookahead/speculation):

Metric	base-1 (conv.)	base-2 (conv.+opt)	Ring (proposed)
Latency	1.00	1.01	0.47 (–53%)
Saturation	1.00	1.08	1.00 (≈)
Area	1.00	1.01	0.66 (–34%)
Power	1.00	1.02	0.73 (–27%)

Versus the enhanced conventional router (base-2), the ring design continues to outperform in latency (16%), area (35%), and power (28%).

6. Design Trade-Offs and Scalability

Ring routing can increase the number of internal hops compared to a crossbar, with typical turns requiring two ring hops and worst-case paths (e.g., N→W) requiring up to four—but this scenario is rare under dimension-order routing. Removing the crossbar reduces area and power at the cost of small local multiplexers and distributed arbitration logic. The logical disjoint at the core exchange, which breaks one VC ring, prevents deadlock with minimal latency penalty.

For a five-port router, the internal ring remains small, and additional ports would linearly increase internal hops, suggesting strong suitability for mesh topologies. Increasing flit width scales both conventional and ring designs linearly, but only the conventional crossbar increases quadratically in area with port count. Further ring expansion—for additional NoC topologies or accelerator connections—is feasible by inserting more exchanges, but increases router pipeline depth and per-hop latency accordingly.

7. Summary and Context

The ring router microarchitecture embodies the concept of an internally-networked router, offering a substantial reduction in physical and energy cost by restructuring the core switching mechanism around a bidirectional ring of exchanges. In standard mesh networks applying dimension-order routing, most packets incur only two internal hops per router. Under direct synthesis and simulation, this approach achieves markedly reduced latency, area, and power compared to both classical and optimized conventional routers. The ring topology is maximally effective for five-port mesh routers and offers a path to incorporating more ports or higher flit widths with more amenable scalability than crossbar-based alternatives (Wu, 2020).