Quantum Sequential Circuits

• Quantum Sequential Circuits (QSCs) are advanced quantum architectures that incorporate explicit temporal sequencing, built-in memory elements, and resource-efficient state preparation protocols.
• They enable the generation of long-range entangled states, such as GHZ and topologically ordered phases, through localized interactions and duality transformations.
• QSC frameworks support scalable simulation, verification, and universal gate synthesis via models like sequential unitary circuits, quantum state machines, and quantum transistor architectures.

Quantum Sequential Circuits (QSCs) encompass a class of quantum information processing architectures characterized by explicit temporal sequencing, inherent memory elements, and specialized resource-efficient state preparation and measurement protocols. QSCs unify concepts from sequential unitary circuits, quantum state machines, channel-state duality, symmetry-protected topological junctions, and reversible circuit design. They address the synthesis, verification, and physical realization of quantum analogs of classical sequential logic systems, the generation of highly entangled states, and support for scalable, modular quantum computation architectures.

1. Foundational Definitions and Models

Quantum Sequential Circuits (QSCs) admit several precise formulations, each illuminating different aspects relevant to computation, simulation, and physical implementation.

Sequential Unitary (SU) Circuits:

QSCs may be framed as linear-depth sequential unitary (SU) circuits, where a “bond” qubit sequentially interacts with an array of data qubits via local two-qubit unitaries. For $N$ qubits, an SU circuit has depth $T = N-1$, with the global unitary composed as

$$\mathcal{U}_{\rm SU} = \prod_{t=1}^{N-1} U_{t, t+1} = U_{N-1, N} \cdots U_{2,3} U_{1,2},$$

where $U_{i,i+1}$ acts only on qubits $i$ and $i+1$ (Lu et al., 16 Jul 2025).

Quantum State Machines (QSMs):

As an abstract model, QSCs are naturally identified with quantum Mealy machines, defined by a tuple $(\mathcal{H}_{\rm in}, \mathcal{H}_s, U, M)$, where $\mathcal{H}_{\rm in}$ is the input Hilbert space, $\mathcal{H}_s$ the internal state (memory), $U$ a unitary on $\mathcal{H}_{\rm in}\otimes\mathcal{H}_s$, and $M$ a POVM measurement on $\mathcal{H}_{\rm in}$ (or the joint space). The system evolves by applying $U$, measuring the inputs, and updating the internal state by tracing out the input subsystem, establishing an explicit temporal sequence akin to classical sequential circuits (Wang et al., 2018).

Quantum Transistor Architecture:

QSCs can also be physically grounded via the quantum transistor, where computation is executed by activating gates encoded as Choi states in symmetry-protected topological (SPT) junctions. In this paradigm, feedback loops are realized using entangled Bell pairs (“ebits”) that connect output and input edge modes across modular circuit elements, supporting internal memory and temporal sequencing (Wang, 5 Feb 2026).

2. Preparation of Long-Range Entangled States and Phase Transitions

QSCs, particularly SU circuits, are powerful tools for generating states with nontrivial long-range entanglement, topological order, and symmetry-breaking via a strictly local, time-ordered protocol.

GHZ State Preparation:

Starting from $\ket{+}^{\otimes N}$, sequentially applying gates of the form

$$u_{i,i+1} = \exp\left(-i \frac{\pi}{4} X_{i+1}\right) \exp\left(-i \frac{\pi}{4} Z_i Z_{i+1}\right)$$

yields the $N$-qubit GHZ state,

$$\ket{\rm GHZ_N} = \frac{1}{\sqrt{2}}\left(\ket{0}^{\otimes N} + \ket{1}^{\otimes N}\right)$$

in depth $O(N)$ (Lu et al., 16 Jul 2025, Chen et al., 2023).

Topologically Ordered and SPT States:

QSCs extend to preparation of $\mathbb{Z}_2$ topological ground states (e.g., toric code) by sweeping plaquette-enforcing gates through the lattice, maintaining area-law entanglement and gappedness. In higher dimensions, sequential circuits build string-net, Walker–Wang, and fracton phases via layer- or row-by-row condensate growth, enabling domain wall/anyon condensation and implementation of Kramers–Wannier dualities (Lu et al., 16 Jul 2025, Chen et al., 2023).

Preservation of Area Law and Gappedness:

Because each qudit participates in only $O(1)$ local unitaries, total entanglement (across any bipartition) grows at most by $O(1)$. Sequential circuits thus map area-law states to area-law states, preserving gapped ground states while constructing nontrivial long-range order (Chen et al., 2023).

3. Duality with Measurement-Feedback Circuits and Protocol Design

A central structural result for QSCs is the spacetime duality between linear-depth SU circuits and constant-depth measurement-feedback (MF) circuits.

Spacetime Rotation:

Any SU circuit can be “rotated” in spacetime to produce an MF circuit comprised of a depth-one local unitary layer, qubitwise projective measurements, and local feedback unitaries. For instance, the sequential Kramers–Wannier circuit generating a GHZ state maps under duality to a constant-depth $\mathbb{Z}_2$ gauging protocol acting on Bell pairs, followed by $X$-measurements and Pauli-$X$ feedback corrections (Lu et al., 16 Jul 2025).

Implications for Resource Trade-offs:

• SU circuits require depth $O(N)$ but only $O(N)$ qubits without feedforward or measurement.
• MF circuits achieve constant depth at the cost of $O(N)$ ancilla measurements and classical feedforward.

Qubit-Efficient Measurements:

The duality enables qubit- and time-efficient schemes for quantum state tomography and order parameter measurement. For example, measurement of highly nonlocal disorder operators in many-body states can be performed using only two qubits by sequentially evolving a “bond” qubit and measuring its autocorrelations (Lu et al., 16 Jul 2025).

4. Verification, Equivalence Checking, and Formal Properties

The correct implementation of QSCs, their equivalence, and their behavior across different architectures are formalized by quantum automata and algorithmic verification.

Equivalence Checking via QSMs:

Two sequential quantum circuits are equivalent if, for all basis input sequences up to a quadratic length in Hilbert space dimension, their output distributions coincide. The core result is that for machines with state dimensions $d_1$ and $d_2$, it suffices to verify equivalence on sequences of length at most $d_1^2 + d_2^2 - 1$, chosen from a fixed basis, rendering the verification problem tractable for small- to moderate-size circuits.

Algorithmic Complexity:

The equivalence-checking algorithm operates with time complexity

$O\big(2^{3m + 5\ell} (2^{3m}+2^{3\ell})\big),$

where $m$ is the number of input qubits and $\ell$ the number of memory qubits in the largest machine. Space complexity is quadratic in Hilbert space dimension. This is comparable to classical state-space approaches (Wang et al., 2018).

5. Circuit Synthesis, Resource Optimization, and Reversible Sequential Elements

QSCs require at their core transparent synthesis strategies and physically meaningful resource metrics, especially for memory elements and classical–quantum interface construction.

Reversible Sequential Elements:

Quantum cost, logical depth (delay), and garbage output number are key metrics for elementary building blocks such as latches (SR, JK, D, T) and flip-flops, constructed via minimal reversible gates including the SAM gate (QC=4). For instance, a master–slave D latch can be synthesized with total quantum cost QC = 11, depth D = 11, and garbage G = 3, representing significant improvements over prior implementations (Mamun et al., 2014).

Reversible Element	Quantum Cost (QC)	Delay (D)	Garbage (G)
Gated D latch	6	6	1
MS-D latch	11	11	3
Gated JK latch	10	10	2

Significance:

Minimizing QC and delay directly lowers hardware resource requirements and error accumulation, while minimizing garbage reduces ancilla and uncomputation overhead. These optimizations directly impact practical, scalable QSC design (Mamun et al., 2014).

6. Quantum Transistor, Memory, and Modular Architectures

The QSC paradigm, especially as instantiated by the quantum transistor, supports modular and hardware-oriented quantum computation with explicit memory management, feedback, and scalable control.

Quantum Transistor Model:

Each transistor is represented by an SPT-protected Choi state, with logical gates accessed via measurements and consumed upon use. Feedback loops are physically instantiated by linking output and input edge modes with ebits, supporting register-like memory and temporal sequencing (Wang, 5 Feb 2026).

Universal Gate Synthesis:

A universal gate set is achieved via combinations of elementary transistors (e.g., Hadamard, Phase, Controlled-$Z$, $T$ via magic-state injection), composed using measurement outcomes and ebit-mediated interconnects. QSCs thus support resource reuse and modular scaling, a quantum analog of the von Neumann architecture.

Comparison to Combinational Circuits:

Unlike combinational (loopless) quantum circuits, QSCs natively incorporate temporal sequencing and quantum memory with explicit feedback, enhancing their expressiveness and physical efficiency (Wang, 5 Feb 2026).

7. Applications, Simulation, and Future Directions

QSC frameworks underpin a range of applications including quantum simulation, phase classification, and experimental protocols for order parameter detection.

Simulation of Many-Body Dynamics:

Layered Uniform Sequential Circuits (l-USCs) provide translation-invariant variational ansätze for infinite systems, matching uniform matrix product state representations but with parameter count scaling only linearly in the entanglement radius (and thus polynomially in simulation time). Hybrid quantum–classical optimization schemes allow for tractable simulation of time evolution on near-term hardware (Astrakhantsev et al., 2022).

Phase Connectivity:

QSCs can map between gapped phases if and only if the phases admit compatible gapped boundaries. All string-net (Levin–Wen) phases with Morita-equivalent fusion categories are SQC-connected, while strictly chiral phases are not (Chen et al., 2023).

Physical Platforms and Challenges:

Implementation prospects include photonic cluster-state arrays, cold-atom SPT chains, and superconducting SPT junctions. Open challenges encompass SPT material engineering, error correction integration, and scalable ebit-interconnect networks while preserving coherence (Wang, 5 Feb 2026).