Quandela's Reconfigurable Photonic Quantum Processor

• Quandela's Reconfigurable Photonic Quantum Processor is an integrated quantum computing platform that combines high-brightness quantum-dot single-photon sources with a universal interferometer for arbitrary quantum circuit implementations.
• It employs precision calibration and machine-learned transpilation to mitigate hardware non-idealities, achieving gate fidelities above 93% in multi-qubit operations.
• The platform supports both gate-based and photon-native computations—including boson sampling and quantum neural network tasks—paving the way for scalable, fault-tolerant photonic processing.

Quandela’s Reconfigurable Photonic Quantum Processor is an integrated quantum computing platform employing single photons routed and manipulated via a universal linear-optical interferometer, realized in a programmable integrated photonic circuit and fed by high-purity, on-demand quantum-dot single-photon sources. The system is designed to implement arbitrary quantum circuits, simulate quantum systems, and perform both gate-based and photon-native quantum computations with fully reconfigurable connectivity, leveraging precision calibration and automated transpilation for hardware-level error mitigation. This architecture integrates advances in large-scale MZI meshes, scalable single-photon source deployment, and automated software stacks, establishing a path for fault-tolerant photonic quantum processing in low-loss, high-fidelity integrated platforms (Maring et al., 2023).

1. Architectural Principles and Hardware Components

Quandela’s processor is structured around a dual combination of a high-brightness quantum-dot single-photon source and a universal photonic interferometer. The quantum-dot source (InGaAs in a micropillar cavity, operated at ≈5 K) is capable of delivering photons at a high repetition rate (80 MHz pump) with a per-pulse brightness of 55%, delivering ~8% quantum efficiency from the source to the chip after fiber coupling and filtering, with a single-photon purity of $g^{(2)}(0) = (7.3 ± 0.1)\times10^{-3}$, corresponding to 99.3% single-photon fraction, and indistinguishabilities above 0.91 for all photon pairs measured via two-photon HOM dips (Maring et al., 2023). The photonic circuit itself is fabricated in low-loss stoichiometric silicon nitride (Si₃N₄) with a 12-mode mesh (Clements-type or rectangular), with 132 directional couplers and 126 thermo-optic phase shifters for universal linear transformations.

Photon inputs are routed via an actively switchable demultiplexer and fiber delays, permitting arbitrary occupation of the spatial modes. Logical qubits are encoded in dual-rail (spatial) encoding: a photon’s presence in either the upper or lower path of a pair defines |0⟩ and |1⟩ states, respectively.

2. Universal Linear Optical Networks and Reconfigurable Control

The linear interferometer is configured as a rectangular mesh, allowing realization of arbitrary 12×12 unitary operators $U$, programmable by setting the voltages on 126 independent thermal phase shifters. Each MZI consists of two directional couplers with mean reflectivity 56.7% (actual), interleaved with phase shifting sections. The full device can route up to 6 indistinguishable single photons through arbitrary quantum optical circuits, implementing gate-level or Fock-state transformations (Maring et al., 2023).

Active calibration is accomplished via a machine-learned phase-and-crosstalk model:

$\vec{\varphi} = A(\vec{V}\odot \vec{V}) + \vec{b}$

where $A$ (126×126) encodes the voltage-to-phase response, including cross-talk, and $\vec{b}$ corrects offsets. Transpilation algorithms globally optimize over these parameters to implement arbitrary target unitary $U$ compensating both cross-talk and non-idealities, leading to mean implementation fidelities of 99.7 ± 0.08% across random $U$ (Maring et al., 2023). Hourly auto-recalibration maintains stability.

3. Quantum Gate Realization, Benchmarking, and Fidelity

Arbitrary single- and multi-qubit operations are realized using dual-rail encoding, with single-qubit rotations constructed from combinations of beam splitters and phase shifters:

• $R_y(\theta)$: Mach–Zehnder composed from two beam splitters and internal phase,
• $R_z(\phi)$: implemented by a single-mode phase shift.

The two-qubit CNOT ("Ralph" post-selected gate) is realized with two ancilla photons and a four-mode subnetwork, with success probability 1/9, and similarly for a three-qubit Toffoli (Maring et al., 2023).

Gate fidelities are assessed by a symmetry-based protocol, expressing the average gate fidelity $F_\mathrm{avg}(U)$ as a sum over measured observables. Reported results:

• One-qubit T-gate: $F_\mathrm{avg}=99.6\pm0.1\%$
• CNOT: $F_\mathrm{avg}=93.8\pm0.6\%$
• Toffoli: $F_\mathrm{avg}=86\pm1.2\%$

State-preparation-and-measurement (SPAM) errors are included, with performance limited primarily by residual multi-photon events and mode mismatch (Maring et al., 2023).

4. Native Photonic Computation: Boson Sampling and Quantum Neural Networks

Photon-native computations are accessible by direct Fock-state injection and detection through the universal interferometer. Six-photon Boson Sampling is demonstrated using a Haar-random unitary, registering 6-photon events at a rate of 0.16 Hz, and validating samples via Aaronson–Arkhipov and likelihood-ratio counter statistics. The total variation distance between observed and ideal output is $D=0.16\pm0.02$, with distribution fidelity $F=0.97\pm0.03$ (Maring et al., 2023).

The processor also hosts hybrid quantum-classical workflows, exemplified by:

• Three-photon quantum neural network classification on the Iris dataset (train accuracy 0.92, test 0.95). Data are encoded as phase shifts, with 32 phase parameters trained classically and quantum outputs measured across pseudo-PNR detection.

5. Reconfigurability, Error Mitigation, and Automated Software Stack

Reconfiguration is realized via a full-stack control suite: the Perceval Python API specifies quantum circuits as either gate-based (logical gates), photonic (mode and Fock input), or direct unitary transformations. The transpilation layer (machine-learned mapping) automatically inverts hardware non-idealities, delivering target operations at the phase-voltage level (Maring et al., 2023).

Device calibration is fully automated and performed hourly. The stack supports batch and interactive cloud workflows, integrating input state preparation, phase programming, data acquisition (SNSPD time-tags), and raw/processed data return.

6. Entangled State Generation and Measurement-Based Computing Primitives

Entanglement generation is a core capability. The device implements heralded three-photon GHZ state preparation using six-photon Fock inputs routed through a three-MZI "GHZ factory." Heralding patterns in the outputs project the post-selected state onto $$|GHZ_3^+\rangle = (|000\rangle + |111\rangle)/\sqrt{2}$$, with measured stabilizer fidelity $F_{GHZ_3^+}=0.82\pm0.04$ (Maring et al., 2023). This capability is a precursory step for measurement-based computing, enabling construction of larger graph states for cluster-state quantum computation.

7. Scalability, Integration Prospects, and Outlook

Scalability is a function of photon source efficiency, loss mitigation, and integrated circuit complexity. Near-term projections target QD brightness over 96%, fiber and filtering above 80%, and on-chip transmission approaching 70%, leveraging 320 MHz pumping for 6-photon rates up to 35 kHz and projected 12-photon events at 10 Hz (Maring et al., 2023). Device architecture is extensible to larger mode meshes (⩾32 modes), with software and hardware integration strategies aligned with the scaling trends in CMOS-compatible silicon photonics and large-scale MZI arrays (Santagati et al., 2017, Taballione et al., 2018).

A plausible implication is that integration of deterministic cluster-state sources and high-speed electro-optic phase modulation, as well as further co-integration of quantum-dot arrays and on-chip single-photon detectors, will further advance the platform to tolerate deeper circuits and fault-tolerant operation, as outlined by the Toulouse-Cambridge blueprints (Ellis et al., 2018).

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Key Bibliography: (Maring et al., 2023, Ellis et al., 2018, Santagati et al., 2017, Saglamyurek et al., 2014, Taballione et al., 2018).