PoTAcc: PoT-Quantized Edge Accelerator

• PoTAcc is an integrated open-source framework that deploys power-of-two quantized DNNs on resource-constrained edge devices by coupling PoT-aware preprocessing with custom shift-based accelerators.
• It converts standard models using schemes like QKeras, APoT, and MSQ, replacing multiplications with efficient bit-shift operations and packing 4-bit weights to halve memory usage.
• Empirical results on FPGA platforms demonstrate notable speedups and energy reductions versus conventional CPU and multiplier-based approaches, emphasizing its practical edge deployment benefits.

PoTAcc is an open-source, end-to-end hardware/software pipeline and accelerator architecture for deploying and accelerating power-of-two (PoT)-quantized deep neural networks on resource-constrained edge devices. Its defining idea is to combine PoT-aware model preparation with shift-based FPGA execution, so that PoT-quantized weights can replace general multiplications with bit-shift operations during inference. In the reported implementations, PoTAcc spans model quantization, TensorFlow Lite conversion, PoT-specific weight preprocessing, accelerator integration, and end-to-end evaluation on heterogeneous CPU-FPGA systems (Saha et al., 2024, Saha et al., 7 May 2026).

1. Problem setting and design rationale

PoTAcc addresses a specific systems gap in low-bit inference. Non-uniform quantization, such as power-of-two quantization, matches data distributions better than uniform quantization, which reduces the quantization error of deep neural networks. PoT quantization also allows bit-shift operations to replace multiplications, but the reported literature identified limited studies on the efficiency of shift-based accelerators for PoT quantization, and an absence of an open-source, end-to-end pipeline that trains or quantizes models, generates an optimized edge deployment, integrates a custom shift-based accelerator, and supports design-space exploration (Saha et al., 2024).

The pipeline is motivated by the mismatch between PoT arithmetic and mainstream deployment stacks. CPUs and GPUs do not provide optimized backends for bit-shift operations, and popular deployment frameworks do not natively support PoT quantization formats. PoTAcc therefore couples PoT-aware preprocessing with custom hardware accelerators, rather than assuming that generic INT8 backends can exploit PoT structure directly (Saha et al., 7 May 2026).

Within this design space, PoTAcc treats PoT quantization not merely as a compression method but as a hardware-software co-design constraint. The central premise is that smaller models, reduced weight bandwidth, and shift-based processing elements can be exploited together only if the quantized representation, runtime format, accelerator datapath, and deployment framework are aligned. This suggests that PoTAcc is best understood as an integration framework rather than as a single quantization scheme.

2. Quantization model and numerical representation

PoT quantization in PoTAcc is a non-uniform quantization in which each quantization level is a power of two or a sum of a few powers of two. A simple per-value mapping is

$$Q(x) = 2^{\lfloor \log_2(x) \rceil}, \quad x \neq 0$$

with shift term $k = \lfloor \log_2(x) \rceil$. Under a single-term PoT scheme, a weight can be written as $w = s \cdot 2^k$, where $s \in \{-1,+1\}$ is the sign bit, so that a multiplication $a \cdot w$ can be implemented by shifting the activation and applying the sign. Under multi-term schemes such as APoT and MSQ, weights take the form $w = s \cdot (2^{k_1} + 2^{k_2})$, which requires two shifts and one addition per multiplication (Saha et al., 2024).

The reported PoTAcc configurations use 4-bit weights and 8-bit activations. In the 2024 pipeline, activations remain uniformly quantized 8-bit integers, while weights use 4-bit PoT quantization. In the 2026 pipeline, PoTAcc focuses on 4-bit PoT weights and 8-bit activations as the TFLite standard, with first and last layers using uniform 8-bit quantization during training setups described for APoT, MSQ, and QKeras (Saha et al., 2024, Saha et al., 7 May 2026).

A key technical distinction is the representation chain used by the later pipeline: pot_float, pot_int, and pot_inte. pot_float denotes the PoT values used during training; pot_int denotes integer PoT values used for efficient shifts; and pot_inte denotes a 4-bit encoded form containing sign plus PoT-term indices, which is the form stored and consumed by the accelerator. PoTAcc preprocesses TFLite int8 weights into this PoT-specific 4-bit representation and packs two weights per byte, halving the weight memory footprint used by the accelerator (Saha et al., 7 May 2026).

The three principal PoT schemes considered by PoTAcc differ in both quantization structure and hardware cost.

Scheme	Quantization structure	Hardware consequence
QKeras PoT	Single-term PoT; sign bit + 3-bit shift value	One shift per weight; no zero term
MSQ	Two PoT terms; zero allowed	Two shifts, one add, extra decode logic
APoT	Two PoT terms; zero allowed; extra remapping logic	Two shifts, one add, more complex muxing

In the 2024 evaluation, the 4-bit QKeras scheme uses quantization levels $\pm2^0$ to $\pm2^7$ after integer mapping; MSQ and APoT use two-term constructions with zero as a valid level and scheme-specific PoT terms. In the 2026 evaluation, QKeras removes 0 as a quantization level to simplify hardware, while APoT and MSQ retain multi-term encodings with zero-term support (Saha et al., 2024, Saha et al., 7 May 2026).

3. Shift-based processing elements and accelerator architecture

A core contribution of PoTAcc is the explicit design and comparison of shift-based processing elements, or shift-PEs, for different PoT quantization methods. The simplest variant is the 8_4_pot_QKeras shift-PE, which takes an 8-bit activation and a 4-bit PoT weight, extracts the sign and 3-bit shift term, shifts the activation, applies sign correction, and accumulates the result. Its datapath is described as one shifter, one mux, and one adder (Saha et al., 2024).

The 8_4_pot_MSQ and 8_4_pot_APoT shift-PEs are more complex because they use two PoT terms per weight. Both require two shifters and an internal addition; both also require zero handling because zero is a valid quantization level but cannot be represented as a literal power of two. APoT adds remapping logic because some effective exponents exceed what can be encoded directly in the allocated bits (Saha et al., 2024).

The 2024 hardware synthesis results on the Zynq platform quantify these design differences. The QKeras shift-PE uses 33 LUTs, 0 FFs, and 1 cycle; the MSQ shift-PE uses 89 LUTs, 17 FFs, and 2 cycles; the APoT shift-PE uses 118 LUTs, 19 FFs, and 3 cycles; and a standard 8-bit multiplier-based PE uses 41 LUTs, 0 FFs, and 2 cycles. Across 27 matrix-multiplication shapes, the QKeras shift-PE achieves 1.60× average speedup and 1.55× average energy reduction versus the 8-bit multiplier-based baseline, while MSQ and APoT also outperform the multiplier-based PE but by smaller margins. On that basis, the QKeras shift-PE is identified as the preferred choice for integration into the full accelerator (Saha et al., 2024).

The accelerator architecture is initially derived from the SECDA-TFLite Vector MAC accelerator. In the 2024 configuration, PoTAcc replaces multiplier-based PEs with QKeras shift-PEs, packs 4-bit weights densely in memory, and deploys four GEMM units with 64 PEs each. Because weight bit-width is halved from 8 bits to 4 bits, twice as many weights can be stored in the on-chip weight buffer, and weight transfer time from DRAM is halved (Saha et al., 2024).

The 2026 paper generalizes this hardware into a Vector-Shift Accumulator, or VSAC, derived from an optimized vector MAC baseline, VMAC_opt. VMAC_opt introduces weight-copy optimization, DMA weight preload, FC-layer support, scalable GEMM counts, and a 64-bit data width for on-chip buffers. VSAC then replaces int8 multiplier PEs with PoT-aware shift-PEs. The reported instantiations use four GEMM units on PYNQ-Z2 and eight GEMM units on Kria KV260, with 200 MHz and 250 MHz FPGA frequencies, respectively (Saha et al., 7 May 2026).

4. Software pipeline, model conversion, and runtime integration

PoTAcc is explicitly presented as an end-to-end pipeline. In the 2024 formulation, its major stages are DNN Model Generation, Accelerator Design, and Inference & Evaluation. The model-generation path starts from a full-precision TensorFlow model, applies PoT quantization via QKeras to targeted convolutional layers, converts the model to TFLite, and then preprocesses TFLite weights into the accelerator’s internal 4-bit shift-term representation (Saha et al., 2024).

The later pipeline broadens the front end to both TensorFlow and PyTorch. QKeras PoT models are converted directly through the TFLite converter. APoT and MSQ models trained in PyTorch are first rewritten so that quantized convolutional and fully connected layers are replaced by standard layers, their stored floating-point weights are re-quantized using the PoT quantizer forward function, and the resulting model is converted from PyTorch to TensorFlow using Nobuco before TFLite conversion (Saha et al., 7 May 2026).

Weight preprocessing is a defining PoTAcc step. Standard TFLite quantization yields int8 weights with a scale $S_w$, but not in PoT-encoded form. PoTAcc therefore performs scale correction so that the quantized values align with the desired pot_int levels, updates bias scale accordingly, encodes the result into 4-bit pot_inte, and packs two weights per byte. In the 2024 QKeras-based flow, this preprocessing maps TFLite’s 8-bit PoT values $\pm 2^k$ to sign bit plus 3-bit shift term over the range 0–7. In the 2026 flow, the same general strategy is extended to APoT and MSQ, where the 4-bit code stores a sign bit and term indices, including a special value for zero terms (Saha et al., 2024, Saha et al., 7 May 2026).

At runtime, PoTAcc uses the TFLite delegate mechanism. Supported CONV and FC operators are delegated to the accelerator; unsupported operations remain on the CPU. In the earlier pipeline, convolution layers are lowered to GEMM and accelerated, while non-convolution layers execute on the ARM Cortex-A9 CPU. In the later pipeline, CONV and FC layers are offloaded, while depthwise convolution, layer norm, attention projections, pooling, softmax, and related operators remain on the CPU. The delegate’s prepare() stage analyzes the graph, preprocesses and preloads weights, and adjusts scales; invoke() performs activation preparation, DMA transfers, accelerator execution, and output copy-back (Saha et al., 2024, Saha et al., 7 May 2026).

5. Empirical evaluation

The 2024 evaluation uses a PYNQ-Z2 board with a dual-core ARM Cortex-A9 CPU and FPGA fabric, with accelerator designs synthesized by Vivado HLS at a target frequency of 250 MHz. Three PoT-quantized ImageNet-class models are reported: MobileNetV2, ResNet18, and InceptionV1. Relative to CPU-only execution, the shift accelerator achieves 1.51× speedup and 1.19× energy reduction on MobileNetV2, 2.85× speedup and 2.13× energy reduction on ResNet18, and 3.03× speedup and 2.17× energy reduction on InceptionV1. Averaged across the three networks, it achieves 1.23× speedup and 1.24× energy reduction compared to the multiplier-based accelerator, and 2.46× speedup and 1.83× energy reduction compared to CPU-only execution (Saha et al., 2024).

The 2026 evaluation expands both the model set and the hardware targets. Reported CNNs include MobileNetV2, InceptionV1, ResNet18, ResNet20, and EfficientNet-Lite; reported vision transformers include ViT_tiny, ViT_small, DeiT_tiny, and DeiT_small. The two target platforms are PYNQ-Z2 and Kria KV260. On PYNQ-Z2, the CPU-accelerator design reports up to 3.6× speedup and 78% energy reduction compared to CPU-only execution for PoT-quantized DNNs, with an average speedup of about 2.3× and an average energy reduction of about 52.6% across the evaluated CNNs and transformers. On Kria, the stronger CPU baseline reduces latency gains, and the reported average speedup versus CPU is around 1.0×, but the average energy reduction is about 29.4% (Saha et al., 7 May 2026).

Accuracy measurements in the later paper emphasize that most loss arises from activation quantization in TFLite rather than from PoTAcc-specific deployment steps. On CIFAR-10, ResNet20 with APoT reports 92.6% Top-1 during training, 92.4% after TFLite int8 conversion, and 92.6% after weight preprocessing and execution on VSAC_APoT; MobileNetV2 with QKeras reports 93.9% during training and 93.5% after conversion and VSAC_QKeras. On ImageNet, ResNet18 with APoT reports 70.2% during training and 69.2% after TFLite plus VSAC_APoT; MobileNetV2 with APoT reports 71.3% during training, 69.5% after TFLite int8, and 69.4% after PoT conversion and VSAC_APoT. The reported average gap between the TFLite int8 version and final PoTAcc deployment is 0.1% (Saha et al., 7 May 2026).

These results also clarify model-dependent behavior. ResNet18 shows the largest gains in the 2024 study because larger convolution layers benefit more from reduced weight bandwidth and higher accelerator utilization. MobileNetV2 shows smaller latency gains in the later study because depthwise convolutions are not accelerated and remain on the CPU (Saha et al., 2024, Saha et al., 7 May 2026).

6. Position within related work, limitations, and outlook

PoTAcc is situated against two main classes of prior work: PoT quantization methods that emphasize accuracy, and hardware proposals that do not provide a complete open-source deployment flow. The cited context includes APoT, MSQ, QKeras PoT, ShiftCNN, JLQ, BS-MUL, DenseShift, DeepShift, TVM/VTA-style mixed-quantization systems, and prior FPGA accelerators. The recurrent limitation identified across those lines of work is that they often stop at training, kernel-level prototypes, or partial hardware demonstrations, do not systematically compare processing-element complexity across PoT schemes at 4 bits, and do not provide a framework-integrated path from quantized models to end-to-end execution on edge devices (Saha et al., 2024, Saha et al., 7 May 2026).

Within that landscape, PoTAcc’s reported novelty lies in three linked properties: systematic hardware analysis of different PoT schemes at the PE level; a shift-based accelerator tuned for 4-bit PoT weights and 8-bit activations; and an open-source pipeline integrated with TFLite and SECDA-TFLite. The later paper extends this by supporting three PoT schemes in a common architecture, two FPGA platforms, both CNNs and transformer-based architectures, and a TFLite delegate for heterogeneous execution (Saha et al., 2024, Saha et al., 7 May 2026).

The limitations are explicitly stated. Operator coverage is restricted: the accelerators handle standard dense CONV and FC layers, while depthwise convolution, pooling, attention-related operators, and layer normalization remain on the CPU. The current dataflow sends activations from CPU to DMA to accelerator and back for each offloaded layer, with no inter-layer reuse of activations within the accelerator. Small FPGAs such as PYNQ-Z2 remain resource-constrained, and on Kria the CPU-only baseline is already strong enough that latency gains can be modest or negative for some models, even when energy improves. Some ImageNet PoT models in the later study are synthetic rather than state-of-the-art PoT-trained networks (Saha et al., 7 May 2026).

The stated future directions follow directly from those constraints: support for more layer types, keeping activations on-chip across consecutive layers, exploration of additional PoT schemes and lower bit-widths such as 2- or 3-bit PoT weights, further optimization of shift-PE design, extension beyond FPGAs to ASIC prototypes, and improved activation quantization. A plausible implication is that PoTAcc’s enduring significance lies less in any single accelerator instance than in establishing a reusable experimental substrate for studying how quantization format, hardware datapath, memory hierarchy, and runtime integration interact in practical edge deployment (Saha et al., 7 May 2026).

PoTAcc’s codebase is reported at https://github.com/gicLAB/PoTAcc, and the repository is described as containing PoT quantization configurations, accelerator design files, integration scripts, drivers, example models, and deployment flows for reproducing the reported experiments and extending them to additional designs (Saha et al., 2024).