Persistent Memory Bank Systems

• Persistent Memory Bank is a durable, shared storage abstraction that retains data and learned knowledge across failures and reboots.
• Architectural designs vary from disaggregated NVM systems with atomic log-based protocols to differentiable neural memory modules with selective update mechanisms.
• Applications span transactional data stores, continual learning in AI, and embodied navigation systems, emphasizing scalability, efficiency, and robust recovery.

A persistent memory bank is a shared, durable, and high-availability storage abstraction that allows multiple systems—classic applications, distributed data stores, or deep neural architectures—to read from and write to a memory store that retains information across failures, reboots, and even user sessions. Unlike volatile main memory or ephemeral neural caches, persistent memory banks ensure that both the data and, in some designs, learned knowledge, are stably maintained and accessible for long-term operation or continual learning. Architectures implementing persistent memory banks span from hardware-centric disaggregated Non-Volatile Memory (NVM) deployments to dense latent-space memory modules in neural networks and experience-based retrieval for embodied AI systems.

1. Architectural Foundations Across Modalities

Systems-level persistent memory banks primarily target rack-scale deployments using high-density byte-addressable NVM, accessed remotely by CPU hosts via high-throughput networks (e.g., InfiniBand supporting RDMA semantics). Representative disaggregated configurations, as in the AsymNVM framework, decouple computation (front-end nodes with only local DRAM) from capacity and durability (back-end NVM blades), enabling resource pooling, failover, and maintenance without data unavailability (Ma et al., 2018). The memory bank is physically realized as one or more NVM devices (back-ends), each exposing a minimal interface—one-sided RDMA for reads, atomic log-based appends for writes, and region allocation handlers. Multi-tenant front ends access the persistent bank with direct, low-latency verbs, decoupling operational logic and caching from persistence and reliability.

In neural architectures, the persistent memory bank abstracts as a differentiable, high-capacity vector store coupled to a frozen LLM or agent, with mechanisms for learned read/write through parameter-efficient adapters. In the “Trained Persistent Memory for Frozen Encoder–Decoder LLMs” framework, the memory bank is a $\mathbb{R}^{n_P \times d}$ array holding latent representations, accumulating over interactions (“conversational learning”) (Jeong, 17 Mar 2026). For embodied agents in navigation, Memoir constructs persistent hybrid viewpoint-level memory banks—overlaying observations and agent behaviors as retrievable states indexed to spatial nodes in a topological graph (Xu et al., 9 Oct 2025).

2. Core Read and Write Protocols

In disaggregated NVM stores, all memory bank updates employ log-structured protocols to guarantee both atomicity and crash consistency. Front-ends batch updates (operation- and memory-level logs), invoke remote atomic append via RDMA, and rely on checksums for integrity; acknowledgments guarantee durability before higher-level commit (Ma et al., 2018). Reads are directly served by RDMA pull, with local DRAM caching reducing remote accesses. Concurrency uses lock-word CAS (single-writer, multi-reader) or lock-free multi-versioning (MVCC).

Data store architectures differ in control and data-flow orchestration: DPM-Direct (all CNs access DPM one-sided, distributed locking), DPM-Central (coordinator serializes all updates, clients are thin), DPM-Sep (CNs perform data path directly, but consult metadata server for control) (Tsai et al., 2019). Only SepDS achieves lock-free commits with version-chaining and asynchronous GC, maximizing throughput at scale while guaranteeing per-entry atomicity.

Neural persistent memory banks implement differentiable write mechanisms: dense attention-weighted key–value updates (soft-attention), Hebbian (associative outer product), or slot-based sparse overwrite, tuned per architecture (Jeong, 17 Mar 2026). Reads combine frozen model queries and adapter-driven cross-attention, with the persistent bank either extending decoder KV, feeding prefix tokens to the encoder, or serving as an explicit memory head.

Experience-centric banks in Memoir augment every environmental transition with zero-overhead append to observation and history banks; retrieval is orchestrated by a learned world model, which “imagines” candidate future states to drive selective memory querying through vector similarity and trajectory matching (Xu et al., 9 Oct 2025).

3. Consistency, Durability, and Recovery

Hardware-centric banks employ crash-consistency primitives: atomic RDMA-write (persisting logs before acknowledgment), replayable redo logs, and checksums ensure that upon any failure, unreplayed partial batches are discarded and the memory is brought to a valid committed state (Ma et al., 2018). Replication of all logs to at least one mirror NVM guarantees durability even upon catastrophic failure. Rapid recovery relies on the combination of authoritative logs and well-known metadata pointers, allowing for efficient allocation and state reconstruction.

For DPM architectures, per-entry atomicity and read-committed guarantees derive from explicit protocol-level synchronization (locks in DPM-Direct, serialized metadata in CentralDS, pointer-chaining and version guards in SepDS) (Tsai et al., 2019). Each system is engineered to prevent exposure of partial or corrupted data, with transactional consistency for single key writes and simple fallback recovery by scanning log regions or authoritative metadata.

Neural persistent banks, being pure software, achieve “durability” with process persistence of the float arrays (backed to disk as needed) and rely on the stability of the adapter parameters (typically only millions of weights, kept in conventional model checkpointing). Since only the persistent bank is mutated at inference, replay or recovery is not needed except to restore a previous memory state. In Memoir, every step’s insertion into the banks is append-only; the system’s learned retrieval is inherently robust to partial database availability since compatibility scores and decay parameters filter for best matches (Xu et al., 9 Oct 2025).

4. Memory Bank Structure and Scaling

Disaggregated NVM banks organize into two main regions per device: a “data” region for authoritative live data structures and a “log” region for operation and modification logs (Ma et al., 2018). Scalability is achieved through resource disaggregation: one or a handful of high-density NVM blades serve tens of stateless compute nodes, with high network utilization yielding data center aggregate utilization far surpassing per-node NVM attachment. The underlying design supports logical many-to-many connectivity and efficient failover.

Neural memory banks use dense matrix storage: in (Jeong, 17 Mar 2026), $P_t \in \mathbb{R}^{n_P \times d}$ uses $n_P=64$ or $640$ slots and $d$ matching the backbone hidden size (e.g., 2048), but are architected for arbitrary scale—thousands to millions of slots with no structural change to the neural backbone. Access cost remains constant per step, as retrieval is independent of total bank size.

Memoir’s bank overlays two interlinked stores: the observation bank (visual features $\mathcal{M}_o$) and the history bank (latent trajectories $\mathcal{M}_h$) tied to a persistent topological graph of viewpoints. Unlike standard episodic memories, Memoir’s structure supports hybrid and associative querying, with unbounded append capacity limited only by storage, not memory constraints (Xu et al., 9 Oct 2025).

5. Caching, Concurrency, and Performance

In AsymNVM, local DRAM on front-end nodes serves as a low-latency cache for “hot” NVM pages, with cache eviction policies combining random sampling and LRU. For data structures like B+Trees or graph stores, only high-access nodes are retained in cache, adaptively tuning cache levels based on observed miss ratio. Batching, operation logs, and caching yield a 6–22$\times$ throughput gain over naïve remote-access baselines, with write-intensive workloads showing speedup factors of 13–16$\times$ over RDMA-only approaches (Ma et al., 2018).

For the DPM store designs, SepDS achieves 1–3 RTT data-path latencies with linear scalability across compute and memory nodes, holding $\sim$90% of peak throughput by caching only 5–10% of metadata locally. DirectDS excels for tiny read-only payloads; CentralDS simplifies implementation but bottlenecks beyond small cluster sizes (Tsai et al., 2019).

Neural persistent banks avoid the exponential growth of context-window methods; per-turn cost remains low because only the memory array is updated, not the backbone. Selective write (slot-based, attention-sparse, or Hebbian) is critical to avoid memory interference at low capacity; experimental results show that only selective schemes retain nonzero recall under tight constraints (Jeong, 17 Mar 2026). For experience retrieval in Memoir, hybrid graph-based memory structures yield 74% reduction in inference memory, 8.3$P_t \in \mathbb{R}^{n_P \times d}$0 training speedup, and significant navigation policy gains across benchmarks compared to full-memory baselines (Xu et al., 9 Oct 2025).

System (Paper)	Scaling Limit	Performance/Throughput
AsymNVM (Ma et al., 2018)	Tens of nodes (rack-scale); bottleneck moves to metadata at $P_t \in \mathbb{R}^{n_P \times d}$1100	6–22$P_t \in \mathbb{R}^{n_P \times d}$2 over baseline, $P_t \in \mathbb{R}^{n_P \times d}$380% scaling with multiple frontends; up to parity with local-NVM
SepDS (Tsai et al., 2019)	14 nodes tested; up to 16 DPMs	1–3 RTT per op, best for mixed workloads, linear scalability
LLM Memory Bank (Jeong, 17 Mar 2026)	Arbitrary (no backbone scaling limit)	Constant step cost; recall $P_t \in \mathbb{R}^{n_P \times d}$418% (short lag, 1$P_t \in \mathbb{R}^{n_P \times d}$5 cap), 7–10% (long lag, 1$P_t \in \mathbb{R}^{n_P \times d}$6 cap)
Memoir (Xu et al., 9 Oct 2025)	Unbounded (storage-limited)	73.5% SPL (20% below oracle); 74% less mem, 8.3$P_t \in \mathbb{R}^{n_P \times d}$7 train speedup

6. Applications and Usage Modes

Persistent memory banks enable multiple advanced workloads:

• Persistent Data Stores: Rack-scale persistent memory services (AsymNVM, DPM stores) support distributed databases, concurrent data structures, and transactional storage with crash recovery, high throughput, and multi-client sharing (Ma et al., 2018, Tsai et al., 2019).
• Machine Learning: Dense persistent memory banks furnish transformer-based LLMs and multimodal agents with continuous, session-spanning memory for retaining, retrieving, and accumulating knowledge (e.g., conversational learning, continual life-long learning) (Jeong, 17 Mar 2026).
• Vision-and-Language Navigation: Systems like Memoir leverage persistent experience banks to enable navigation agents to recall, imagine, and adapt using observed and behavioral histories, attaining both task improvement and substantial efficiency (Xu et al., 9 Oct 2025).

A plausible implication is that persistent memory banks, especially in neural settings, open routes for “episodic” and “semantic” system analogues, bridging hardware and software approaches to knowledge and state persistence.

7. Challenges, Limitations, and Future Directions

Primary challenges arise in metadata management, network scaling, and adaptation under heterogeneous hardware. AsymNVM performance depends on low-latency, high-BW networks; extending strong consistency to multi-writer/multi-reader semantics will require distributed transactional protocols (Raft, Paxos) (Ma et al., 2018). DPM scaling encounters complexity in client-side caching and chain management; CPF bottlenecks appear in very large clusters (Tsai et al., 2019).

For neural banks, selective and interference-robust write/read mechanisms are critical; capacity is a dominant bottleneck at small scale. Full utility demands joint (end-to-end) training of backbone and memory adapters at much greater memory scales and data diversity (Jeong, 17 Mar 2026). In the experience-replay domain, the upper bound between current retrieval and oracle access indicates substantial room for advances in world-model quality and retrieval alignment (Xu et al., 9 Oct 2025).

Ongoing directions include hardware-hardening of back-end APIs, leveraging emerging persistent memory tiers (SSDs, DRAM, NVM), deployment in very large distributed systems, and fully end-to-end learned persistent banks tailored for high-level continual learning objectives.

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References:

• A Case for Asymmetric Non-Volatile Memory Architecture (Ma et al., 2018)
• Trained Persistent Memory for Frozen Encoder–Decoder LLMs: Six Architectural Methods (Jeong, 17 Mar 2026)
• Dream to Recall: Imagination-Guided Experience Retrieval for Memory-Persistent Vision-and-Language Navigation (Xu et al., 9 Oct 2025)
• Building Atomic, Crash-Consistent Data Stores with Disaggregated Persistent Memory (Tsai et al., 2019)