Parallelized Belief Propagation Decoder

• Parallelized belief propagation decoders are architectures that preserve local BP message passing while exploiting concurrency in intra-stage, inter-frame, and branch-level operations.
• They employ diverse methods such as stage parallelism in polar codes, GPU batching for LDPC codes, and speculative reruns in quantum LDPC decoding to enhance speed and efficiency.
• These designs balance trade-offs between maximal parallelism and convergence through adaptive scheduling, graph permutation techniques, and hybrid decoding strategies.

A parallelized belief propagation decoder is a decoder architecture in which the local message-passing structure of belief propagation (BP) is preserved, while concurrency is exploited at one or more levels of the computation: within a graph stage, across edges or nodes, across multiple codewords, across multiple graph or parity-check representations, or across speculative decoding branches. In the literature, this designation covers several distinct but related designs: stage-parallel BP for polar codes, GPU-oriented LDPC decoders that batch many codewords, list decoders that run multiple independent BP instances on permuted graphs, branch-parallel post-processing for quantum LDPC codes, and block-structured BP used as an approximate tensor-network contraction engine for the surface code (Abbas et al., 2015, Zhao et al., 2012, Wang et al., 30 Jun 2025, Kaufmann et al., 2024).

1. Computational model

At its core, BP is an iterative message-passing algorithm on a sparse graphical representation of a code or inference problem. In polar-code BP decoding, the graph is an $m$-stage factor graph for a length-$n=2^m$ code, with $n(m+1)$ nodes and two directional messages per node, $L_{i,j}^t$ and $R_{i,j}^t$; each stage contains $n/2$ processing elements, and many processing elements in the same stage can operate simultaneously (Abbas et al., 2015). In generic many-core BP formulations, the same idea is expressed as a frontier-based bulk-synchronous loop: generate an active set of messages, update the frontier in parallel, test convergence, and repeat (Merwe et al., 2019).

The same message-passing abstraction also appears outside Tanner and factor graphs. In the surface-code blockBP decoder, BP is run on a graph induced by blocks of a tensor network rather than on the code’s Tanner graph directly; the local update has the same form of contracting a node or block against incoming messages from all neighbors except the target neighbor (Kaufmann et al., 2024). This breadth of formulations explains why “parallelized BP decoder” is not a single algorithmic object but a class of decoders that share iterative local inference and differ mainly in where concurrency is exposed.

2. Forms of parallelization

The literature distinguishes several recurring forms of parallelism. Some are intrinsic to a single BP graph, while others arise by replicating BP across alternative graph realizations or candidate hypotheses.

Parallelization mode	Representative mechanism	Example
Stage or edge parallelism	Simultaneous updates for all processing elements in a stage or all active edges	Polar BPD (Abbas et al., 2015)
Inter-frame batching	$\Gamma$ codewords decoded together with edge-aligned message packages	GPU LDPC decoder (Zhao et al., 2012)
List or branch parallelism	Independent BP instances on different graph or matrix variants	BPL and MBBP-LD (Elkelesh et al., 2018, Rabeti et al., 13 May 2026)
Speculative parallelism	Parallel low-iteration reruns on modified unreliable-bit hypotheses	qLDPC post-processing (Wang et al., 30 Jun 2025)
Adaptive branch search	Parallel WMS/WBP branches with different weight schedules	Adaptive learned BP (Tasdighi et al., 26 Jul 2025)
Block parallelism	Message passing between tensor-network blocks	blockBP (Kaufmann et al., 2024)

Intra-graph parallelism is the classical case. For polar codes, all processing elements in the same stage can be evaluated simultaneously, which is why BPD is described as parallel in nature (Abbas et al., 2015). Inter-frame parallelism is exemplified by the GPU LDPC implementation in which $\Gamma$ codewords are decoded together; messages for the same Tanner-graph edge across the $\Gamma$ codewords are grouped into one package and stored linearly, so reads and writes become highly parallel and thread divergence is minimized (Zhao et al., 2012).

A second major pattern is inter-decoder parallelism. In belief propagation list decoding for polar codes, $L$ parallel independent BP decoders run on differently permuted factor graphs and generate a candidate list, after which the codeword closest to the received vector in Euclidean distance is selected (Elkelesh et al., 2018). In the Multiple-Bases Belief-Propagation List Decoder for QLDPC codes, several BP decoders run in parallel on augmented matrices $n=2^m$0, where $n=2^m$1 is drawn from a cycle-free subtree decomposition; successful branch outputs are fused by Frequency-Weighted Scoring (Rabeti et al., 13 May 2026). A related but more adaptive pattern appears in weighted BP: multiple WMS branches with different discrete weight vectors $n=2^m$2 are run in parallel, and the branch with minimum syndrome Hamming weight is selected (Tasdighi et al., 26 Jul 2025).

A third pattern is speculative concurrency after BP failure. For qLDPC codes, one proposed decoder identifies unreliable qubits from BP oscillation statistics, generates Chase-style modified test patterns, and launches many low-iteration BP instances concurrently; the branches are independent once the test patterns are fixed (Wang et al., 30 Jun 2025). This architecture is fully parallelized at the post-processing level even though each constituent BP run remains iterative.

3. Scheduling, convergence, and the limits of maximal parallelism

Parallelization does not eliminate the importance of message scheduling. The standard flooding schedule updates all messages of one class before the next class. In the surface-code partial-decoder work, the implemented “parallel” BP version updates all check-to-error messages before error-to-check messages (Caune et al., 2023). In QLDPC decoding, flooding is likewise defined as updating all check-node messages in parallel and then all variable-node messages in parallel within each iteration (Moradi et al., 10 Mar 2026).

Several studies show that maximal parallelism is not always the best convergence strategy. On GPUs, message scheduling exhibits a tradeoff between speed and convergence: increasing parallelism gives more speed but less convergence, while decreasing parallelism improves convergence but slows execution (Merwe et al., 2019). Exact residual-based top-$n=2^m$3 scheduling is especially unattractive on many-core hardware because sort-and-select can consume more than $n=2^m$4 of runtime and up to $n=2^m$5 in some runs; Randomized BP was introduced to replace exact top-$n=2^m$6 selection with residual thresholding and randomized subsampling, and on the Ising $n=2^m$7 task it yielded average $n=2^m$8 speedups over GPU loopy BP runtimes (Merwe et al., 2019).

QLDPC decoding pushes this point further. A reinforcement-learning-guided sequential scheduler was proposed specifically because flooding BP performs poorly under quantum degeneracy and short cycles; the learned sequential schedule outperformed both flooding and random sequential schedules in convergence speed and frame-error performance at comparable complexity (Moradi et al., 10 Mar 2026). This suggests that a parallelized BP decoder is often best understood as an architecture that exposes concurrency where it is useful, rather than as a decoder that always updates the largest possible set of messages simultaneously.

4. Polar-code realizations

Parallelized BP decoders are especially developed in the polar-code literature. Conventional BPD already has stage-level concurrency, but its main drawback is that every processing element remains active for every iteration unless a stopping rule intervenes. A lower-complexity design introduces connected sub-factor-graph freezing: if a connected sub-factor graph can correctly decode its constituent code, it is frozen, no further message passing is performed inside it, and its feedback messages are fixed to $n=2^m$9 (Abbas et al., 2015). For the $n(m+1)$0 polar code over AWGN with BPSK, min-sum decoding, $n(m+1)$1, and $n(m+1)$2, this scheme showed no performance degradation and, at $n(m+1)$3 dB, reduced average iterations by $n(m+1)$4 versus baseline BPD and $n(m+1)$5 versus G-matrix early stopping; average computation complexity was reduced by $n(m+1)$6 versus baseline BPD and $n(m+1)$7 versus G-matrix early stopping (Abbas et al., 2015).

A different line of work uses graph diversity rather than intra-graph freezing. Belief Propagation List decoding instantiates multiple independent BP decoders on different permuted factor graphs of the same polar code; all decoders use the same observations and frozen set, but each follows a distinct loopy trajectory, and the final output is chosen by the channel-likelihood or Euclidean-distance criterion (Elkelesh et al., 2018). Because the list entries are independent, this form of parallelization is architecturally clean and can approach the finite-length performance of SCL while preserving BP’s regularity and soft-output structure (Elkelesh et al., 2018).

The hardware realization of this idea is developed further in a flexible BPL architecture. A sequential generation algorithm selects a near-optimal set of permuted factor graphs, and a theorem-based permutation network decomposes arbitrary graph permutations into fixed routings, enabling on-the-fly permutation generation (Ren et al., 2022). For length-1024 polar codes with rate one-half, the implemented BPL decoder with 32 permuted factor graphs achieved 25.63 Gbps throughput and 29.46 Gbps/mm$n(m+1)$8 area efficiency at SNR $n(m+1)$9 dB, in 28 nm FD-SOI at 1333 MHz, with average latency 53.25 clock cycles (Ren et al., 2022). This design also shows that a parallelized BP decoder need not instantiate one full BP engine per list entry; a single highly parallel BP core can be combined with overlapped permutation generation and recovery to obtain list-decoding gains (Ren et al., 2022).

A related refinement is partially permuted multi-trellis BP, which permutes only a subgraph rather than the full factor graph. Because only the modified subgraph is reset, messages in unmodified regions are retained, more frequent permutations become possible, and for $L_{i,j}^t$0, $L_{i,j}^t$1, and FER $L_{i,j}^t$2, the scheme reported a $L_{i,j}^t$3 dB gain over full-permutation multi-trellis BP together with reduced latency in terms of the number of iterations (Ranasinghe et al., 2019).

5. LDPC, QLDPC, and surface-code realizations

For classical LDPC codes, one of the earliest large-scale implementations of parallel BP on GPUs decoded $L_{i,j}^t$4 codewords together and packed the $L_{i,j}^t$5 messages associated with the same Tanner-graph edge into one contiguous package (Zhao et al., 2012). With optimized message layout and a thread hierarchy chosen to minimize divergence, the GPU-based LDPC decoder obtained hundreds of times speedup compared with a serial CPU-based simulator and over 40 times speedup compared with an 8-thread CPU-based simulator (Zhao et al., 2012). This work established the now-standard distinction between algorithmic BP parallelism and memory-layout-driven many-core efficiency.

Parallelization can also target the communication fabric itself. Relaxed Half-Stochastic BP for LDPC codes enforces binary inter-node communication while retaining soft state inside variable nodes; check nodes reduce to XOR operations, and the design is aimed explicitly at fully-parallel circuit implementations in which binary messages reduce the number and length of wires and increase logic density (Leduc-Primeau et al., 2012). This architecture addresses a different bottleneck than GPU batching: not arithmetic throughput, but wire count, routing congestion, and logic density in fully parallel hardware (Leduc-Primeau et al., 2012).

Quantum LDPC decoding has produced several branch-parallel BP designs. In one fully parallelized post-processing decoder, a failed BP run is followed by a Chase-style ensemble of short BP reruns on test patterns derived from BP oscillation statistics; the method can achieve logical error rates comparable to or better than BP-OSD while offering lower latency through branch parallelization (Wang et al., 30 Jun 2025). In Multiple-Bases BP List Decoding, redundant parity-check representations are constructed by cycle-free subtree decompositions, several BP decoders operate in parallel on the resulting matrices, and the latency under parallel implementation remains of BP order because it is governed by the slowest branch rather than by the sum of branch runtimes (Rabeti et al., 13 May 2026). For bivariate bicycle codes $L_{i,j}^t$6 and $L_{i,j}^t$7, the decoder achieved up to $L_{i,j}^t$8 reduction in error rate compared to BPGD and up to $L_{i,j}^t$9 compared to BP-OSD in the low- and moderate-error regimes (Rabeti et al., 13 May 2026).

For the surface code, parallelized BP has also entered the degenerate maximum-likelihood setting. The blockBP decoder partitions each logical-coset tensor network into blocks and runs BP between blocks, using block-local boundary-MPS contractions to update messages (Kaufmann et al., 2024). A chessboard schedule permits all blocks of one color to update in parallel, and the decoder was reported to outperform MWPM for a large range of lattice sizes and noise levels, sometimes by more than an order of magnitude in logical error probability (Kaufmann et al., 2024). Here BP is not operating on the Tanner graph of the code; it is operating as a parallelized approximate tensor-network contraction engine (Kaufmann et al., 2024).

6. Hybrids, terminology, and limitations

Parallelized BP is frequently used as a component rather than as a complete decoder. In a two-stage surface-code decoder, BP acts as a partial decoder that corrects high-probability errors and leaves a residual syndrome to MWPM; the paper reports that partial decoding speeds up the MWPM stage by between $R_{i,j}^t$0 and $R_{i,j}^t$1 on average depending on the parameter regime, and raises the threshold from $R_{i,j}^t$2 to $R_{i,j}^t$3 (Caune et al., 2023). At the same time, that work explicitly neglects the runtime of BP itself and justifies the benchmark only under the assumption of a highly parallelised dedicated hardware implementation for BP (Caune et al., 2023). This is a recurring limitation in the area: speedup claims often depend on the distinction between total work and critical-path latency.

A second limitation is terminological. In one surface-code threshold-estimation study, “parallelization” referred to the Monte Carlo benchmarking framework rather than to the internal structure of the BP decoder; decoding remained on CPU, and at $R_{i,j}^t$4, $R_{i,j}^t$5, BP had runtime $R_{i,j}^t$6 s and LER $R_{i,j}^t$7, compared with MWPM at $R_{i,j}^t$8 s and $R_{i,j}^t$9 (Wayo et al., 25 Mar 2026). This makes clear that “parallelized BP decoder” can denote at least three different things in the literature: a decoder with internally parallel message updates, a decoder that runs several BP instances in parallel, or an evaluation harness that parallelizes simulation while leaving the decoder itself unchanged (Wayo et al., 25 Mar 2026).

Two broader conclusions follow. First, maximal internal parallelism is not synonymous with the best decoder: flooding schedules, randomized frontiers, sequential learned schedulers, and speculative branch ensembles all occupy different points on a tradeoff surface defined by convergence, latency, total work, memory traffic, and hardware regularity (Merwe et al., 2019, Moradi et al., 10 Mar 2026). Second, the most successful parallelized BP decoders usually exploit more than one form of concurrency at once: local message-update parallelism, branch-level independence, graph-representation diversity, and overlap between decoding and auxiliary tasks such as permutation generation or block contraction (Ren et al., 2022, Kaufmann et al., 2024). This suggests that the defining feature of the subject is not any single update rule, but a systems-level strategy for exposing concurrency without abandoning BP’s local inferential structure.