OpenDPDv2: Neural DPD for RF Transmitters

• OpenDPDv2 is an integrated neural network-based digital predistortion framework focused on high-fidelity RF PA linearization and energy-efficient deployment.
• It employs advanced PA behavioral modeling with cascaded inverse learning and a novel TRes-DeltaGRU architecture for precise compensation of nonlinearities.
• The framework leverages fixed-point quantization and dynamic temporal sparsity to reduce inference energy by up to 4.5× while maintaining spectral compliance.

OpenDPDv2 is an integrated neural network-based digital predistortion (DPD) framework aimed at high-fidelity linearization and energy-efficient deployment in wideband radio frequency (RF) transmitter systems. Built to support advanced power amplifier (PA) modeling, innovative DPD learning, and hardware-aware model optimization, OpenDPDv2 couples algorithmic improvements with practical implementation strategies, addressing the growing energy demands of next-generation wideband wireless transmitters (Wu et al., 9 Jul 2025).

1. Problem Scope and Motivation

High-throughput RF PAs, especially those processing signals with 200 MHz bandwidth and high-order modulation formats such as 256-QAM OFDM, introduce significant static and dynamic nonlinearities, degrading in-band error vector magnitude (EVM) and generating high out-of-band adjacent channel power ratio (ACPR). DPD, which aims to pre-compensate these nonlinearities at baseband, is essential for spectral compliance and system performance.

Conventional polynomial DPD structures (e.g., Memory Polynomial, GMP) lose effectiveness in ultra-wideband settings, whereas neural network (NN) DPDs achieve the required linearization but at the expense of increased parameter complexity and digital inference power. For real-time streaming transmitters, the DPD inference power ($P_{\mathrm{INF}}$) sharply dominates the total DPD power budget, scaling as $P_{\mathrm{INF}} = E_F \cdot f_s$, where $E_F$ is the per-sample forward-pass energy and $f_s$ the baseband sampling rate (Wu et al., 9 Jul 2025).

OpenDPDv2 addresses three objectives:

• Unified end-to-end PyTorch-based framework for PA modeling and DPD learning,
• State-of-the-art DPD neural architecture combining linearization efficacy and hardware suitability,
• Two orthogonal energy-reduction techniques: fixed-point quantization and dynamic temporal sparsity.

2. Framework Architecture and Learning Methodology

2.1 PA Behavioral Modeling

Given a complex baseband input-output sequence pair $\{\mathbf{X}, \mathbf{Y}\}$, OpenDPDv2 uses deep sequence models trained via back-propagation through time (BPTT) to fit a nominal PA behavioral model, minimizing the mean squared error:

$$\mathcal{L}_{PA} = \frac{1}{T} \sum_{t=0}^{T-1} \| \pi_{PA}(x_t) - y_t \|^2.$$

This provides a differentiable surrogate PA that substitutes for expensive hardware-in-the-loop steps during DPD training.

2.2 DPD Learning via Cascaded Inverse Modeling

The DPD block, denoted $\pi_{DPD}$, is placed in series with the frozen PA model. During learning, the objective is to match the cascade output $\pi_{CAS}(x_t) = \pi_{PA}(\pi_{DPD}(x_t))$ to a scaled linear reference $G x_t$, via

$$\mathcal{L}_{DPD} = \frac{1}{T} \sum_{t=0}^{T-1} \| \pi_{CAS}(x_t) - G x_t \|^2.$$

All optimization is performed offline within PyTorch, storing models attaining the best ACPR performance (Wu et al., 9 Jul 2025).

3. TRes-DeltaGRU Neural DPD Algorithm

The central DPD neural block in OpenDPDv2 is the TRes-DeltaGRU architecture, which fuses a thresholded-delta modification of the gated recurrent unit (GRU) with an auxiliary temporal-convolutional residual (TRes) branch:

• Input Features: At each time step $P_{\mathrm{INF}} = E_F \cdot f_s$0, the feature vector is $P_{\mathrm{INF}} = E_F \cdot f_s$1.
• Delta Operator: For any signal $P_{\mathrm{INF}} = E_F \cdot f_s$2, the delta is:

$P_{\mathrm{INF}} = E_F \cdot f_s$3

Memory $P_{\mathrm{INF}} = E_F \cdot f_s$4 updates only when the threshold is exceeded, separately applied to input features ($P_{\mathrm{INF}} = E_F \cdot f_s$5) and hidden states ($P_{\mathrm{INF}} = E_F \cdot f_s$6).

• Delta-GRU Updates: Pre-activations and gates evolve as

$P_{\mathrm{INF}} = E_F \cdot f_s$7

The GRU state at $P_{\mathrm{INF}} = E_F \cdot f_s$8 proceeds via

$P_{\mathrm{INF}} = E_F \cdot f_s$9

• TRes Path: A two-layer dilated 1D temporal convolutional network applies a residual correction using the input window $E_F$0. The output at $E_F$1 is

$E_F$2

This architecture achieves fine-grained memory modeling with fewer parameters and is amenable to energy-saving optimizations (Wu et al., 9 Jul 2025).

4. Energy Optimization Techniques

Energy efficiency in OpenDPDv2 leverages two complementary strategies, directly targeting the DPD inference bottleneck on digital hardware.

4.1 Fixed-Point Quantization

Each network weight or activation is quantized to $E_F$3 bits by

$E_F$4

where $E_F$5, $E_F$6, and layerwise scale $E_F$7 is trained and constrained to powers of two. Supported quantizations in experiments include 32, 16, and 12 bits for both weights and activations (W32A32, W16A16, W12A12).

4.2 Dynamic Temporal Sparsity

By enforcing thresholds $E_F$8, $E_F$9 on input and hidden deltas, only $f_s$0 fraction of columns in each weight matrix participate in matrix-vector multiplies (M×V), with $f_s$1 denoting the temporal sparsity (fraction of time and features/neurons with zero delta). Inference implementations transparently skip multiply–accumulate (MAC) and memory load operations for these inactive columns, functionally reducing complexity to sparse-vector multiplies (M×SV).

4.3 Overall Energy Model

On ARMv7-A-class hardware, per-sample forward energy decomposes as

$f_s$2

with scaling for bit-width $f_s$3 and sparsity $f_s$4:

$f_s$5

Combining INT12 quantization ($f_s$6) with $f_s$7 sparsity yields a measured $f_s$8 reduction in inference energy compared to FP32 (Wu et al., 9 Jul 2025).

5. Empirical Results and Performance Metrics

OpenDPDv2's benchmarking, using a TM3.1a 200 MHz, 256-QAM OFDM test waveform and a 3.5 GHz GaN Doherty PA, demonstrates both state-of-the-art linearization and substantial energy savings:

Model	Sparsity	Params	Precision	ACPR (dBc)	EVM (dB)	Energy Red.
No DPD	–	–	–	-28.6	-22.7	1×
TRes-DeltaGRU-996 (FP32)	0%	996	FP32	-59.4	-42.1	1×
TRes-DeltaGRU-996 (W12A12)	0%	996	INT12	-54.5	-37.3	2.8×
TRes-DeltaGRU-450 (W12A12)	56%	450	INT12	-50.3	-35.2	4.5×

The compressed TRes-DeltaGRU-450 model, with $f_s$9 temporal sparsity and 12-bit quantization, achieves ACPR $\{\mathbf{X}, \mathbf{Y}\}$0 dBc and EVM $\{\mathbf{X}, \mathbf{Y}\}$1 dB, surpassing wideband linearization thresholds ($\{\mathbf{X}, \mathbf{Y}\}$2 dBc, $\{\mathbf{X}, \mathbf{Y}\}$3 dB) while cutting forward-pass energy by more than fourfold (Wu et al., 9 Jul 2025).

6. Implementation, Datasets, and Reproducibility

The OpenDPDv2 framework is implemented end-to-end in PyTorch, with training, quantization, and sparsity algorithms codified. Evaluation includes real-world energy measurement via compiled C inference kernels simulated on ARMv7-A (7 nm), combined with direct PA linearization tests in the physical lab.

• Dataset: APA_200MHz, derived from 98,304 labeled I/Q samples (60% train / 20% validation / 20% test).
• Training: 240 epochs, AdamW optimizer ($\{\mathbf{X}, \mathbf{Y}\}$4), batch size 64, with dynamic learning rate scheduling in PyTorch 2.4.1.
• Hardware: Ampleon 3.5 GHz GaN Doherty PA at 41.5 dBm, signal sampled at $\{\mathbf{X}, \mathbf{Y}\}$5 MHz.
• Code and Documentation: Available at https://github.com/lab-emi/OpenDPD for reproducibility, including tutorials, energy analysis scripts, and testbench drivers (Wu et al., 9 Jul 2025).

7. Context and Significance

OpenDPDv2 defines an extensible baseline for NN DPD deployment under hardware constraints. Its combination of thresholded-delta RNNs, temporal-convolutional modules, and jointly optimized quantization and temporal sparsity yields high linearization with efficient digital inference. The open-source release—including code, data, and ARM simulation suite—enables benchmarking for both algorithmic research and hardware-aware design in RF transmitter systems.

The framework establishes quantifiable trade-offs between model size, dynamic activation, hardware efficiency, and achievable spectral performance. Its approach is distinct in co-optimizing for RF linearization and digital front-end energy cost, motivating further exploration of neural baseband processing architectures under real-world systems constraints (Wu et al., 9 Jul 2025).