NVIDIA cuLitho: GPU-Native Lithography

• NVIDIA cuLitho is a fully GPU-native computational lithography platform that re-implements OPC primitives and integrates physics-aware AI surrogates to overcome CPU bottlenecks.
• It combines accelerated computing elements like batched FFTs, high-throughput computational geometry, and GPU-resident workflows to achieve 57× end-to-end acceleration.
• Silicon validation demonstrates enhanced process windows and reduced critical dimension errors, leading to significant energy, cost, and CO2 emission benefits.

Searching arXiv for the specified paper and any directly relevant supporting context. NVIDIA cuLitho is a computational lithography platform described as the first fully end-to-end GPU-native implementation of the domain, combining accelerated computing (AC) with physics-aware AI surrogates to overcome the Amdahl’s-law ceiling that limited earlier partial GPU ports. In the reported formulation, cuLitho re-implements the major primitives of optical proximity correction (OPC) and related mask-processing workflows on the GPU, keeps the pipeline resident in device DRAM until final output, and uses AI as a learned initializer for mask-segment movement prediction. The system is presented as achieving a 57× end-to-end acceleration while preserving lithographic accuracy, and as expanding the feasible solution space to include curvilinear masks, high-NA EUV modeling, sub-angstrom feature modeling, and through-focus correction with silicon-validated benefits (Mukhopadhyay et al., 27 Jan 2026).

1. Historical positioning and problem setting

Computational lithography is identified as the largest workload in semiconductor manufacturing, and its complexity is described as having increased sharply in the angstrom-era because of more accurate modeling requirements, more intricate corrections, and broader solution-space exploration. The paper situates cuLitho within a broader AC+AI paradigm for scientific computing, motivated by the claim that growth in workload demand has outpaced transistor scaling and produced unsustainably rising costs, energy consumption, and emissions (Mukhopadhyay et al., 27 Jan 2026).

The specific bottleneck cuLitho addresses is the incompleteness of earlier heterogeneous lithography stacks. Traditional flows in which only optics simulators were ported to the GPU are described as encountering a hard 2× ceiling because approximately half of runtime remained on the CPU in geometry processing, mask rule checking, Boolean operations, contouring, and related stages. cuLitho is therefore framed not as an accelerator for a single kernel, but as a redesign of the software stack around device-aware end-to-end execution.

This positioning also clarifies a common misconception: cuLitho is not presented as a mere optics offload path. Its defining claim is that all major primitives are re-implemented on the GPU and augmented with AI surrogates, so that the platform addresses both the computationally dominant optical kernels and the non-optical stages that previously preserved the serial bottleneck.

2. Heterogeneous architecture and GPU-resident workflow

At the architectural level, cuLitho is described as a heterogeneous, device-aware system whose principal design decision is to keep the entire OPC pipeline GPU-resident. Data do not leave device DRAM until final output, which eliminates PCIe or NVLink transfers and is reported to preserve occupancy. The implementation recasts each OPC building block as a warp-friendly kernel or library, including diffractive optics, computational geometry, mask-rule checks, contour extraction, and measurements (Mukhopadhyay et al., 27 Jan 2026).

The reported AC integration consists of four major elements. Diffractive optics are implemented via batched FFTs and convolution. Computational geometry is implemented through high-throughput bounding-volume hierarchy construction and traversal together with spatial hashing. Mask-rule checks use concurrent neighbor queries and thread-coordinated constraint enforcement. Contour extraction and measurements use massively parallel marching squares and distance queries.

AI is integrated as a high-fidelity surrogate rather than as a replacement for the physics engine. A conditional GAN-UNet ingests the target design, aerial image, and mask-gradient context, and predicts near-final mask segment displacements. These predicted displacements are applied directly to the Manhattan polygon layout, with no curvilinear edges and no post-processing. The paper states that the resulting AI-initialized mask satisfies all MRC constraints and cuts OPC iterations in half.

This architecture suggests a division of labor in which AC expands the available compute envelope by accelerating the full primitive set, while AI reduces solver effort by improving initialization. The reported outcome is not merely lower latency per iteration, but lower iteration count as well.

3. Imaging model and core primitive implementations

The imaging model is based on the Hopkins formulation for partially coherent illumination. In the notation given, the aerial or effective image is expressed as

$$I(r;F,D)=D\iint\iint O_{EM}(f_1)\,O_{EM}^*(f_2)\,TCC(f_1,f_2;F)\,e^{i2\pi r\cdot(f_1-f_2)}\,df_1\,df_2.$$

Here, $O_{EM}(f,o,p)$ is the 3D mask response from rigorous electromagnetic near-field solvers. The transmission cross coefficient is defined as

$$TCC(f_1,f_2;F)=\int S(o)\,P(f_1+o;F)\,P^*(f_2+o;F)\,do,$$

and is reported to be Hermitian positive-semidefinite. cuLitho therefore applies an SVD decomposition,

$$TCC(f_1,f_2)=\sum_k \lambda_k\,\Phi_k(f_1)\,\Phi_k^*(f_2),$$

which yields a coherent-mode expansion,

$I(r)=\sum_k \lambda_k |O_{EM}\ast \Phi_k|^2(r).$

On GPUs, each coherent mode is computed through cuFFT-accelerated forward and inverse transforms with complex multiplication, exploiting locality and memory bandwidth; typical per-mode speedups are reported as exceeding 200× over CPU (Mukhopadhyay et al., 27 Jan 2026).

The computational geometry engine is described as supporting arbitrary, non-Manhattan, self-intersecting, and degenerate polygons through a parallelized plane-sweep-in-parallel method built on a binary radix LBVH. The key steps are Morton-code sorting of edge centroids via radix sort, top-down LBVH construction with fine-requantization when Morton keys collapse, and stack-based depth-first BVH traversal per thread followed by local plane-sweep within leaves. Edge-intersection finding, described as formerly $O(n^2)$, is said to prune 99% of pairs in bounding volumes and to achieve 34×–165× speedups depending on layout density. The same BVH structure is reused for spatial queries such as neighbor searches for MRC, delivering 165× gains versus CPU.

Data-processing kernels are likewise moved to the GPU. Resist convolution, thresholding, contour extraction, and point-to-segment distance queries are implemented as custom CUDA kernels. Interpolation and filtering in the resist model are fused via tensor cores. Marching Squares is executed per grid cell with a reported 176× speedup, and distance queries again use the BVH with a reported 165× gain. Pinned host buffers and in-GPU frontiers are used to eliminate host-GPU transfers.

4. OPC objective, through-focus formulation, and AI initialization

cuLitho formulates OPC as an optimization over mask segment positions $x$ that minimizes an integrated edge placement error subject to mask-rule constraints:

$$\min_x \sum_r \mathrm{EPE}(r)\quad\text{s.t. mask-rule constraints}.$$

The local edge placement error is given as

$$\mathrm{EPE}(r)=\frac{E_\text{eff}(r)-E_\text{target}(r)}{\|\nabla E_\text{eff}(r)\|}.$$

The resist and contour model is summarized through the threshold-contour expression

$$C=\{r\mid (I\ast K_\text{resist})(r)=T_\text{eff}\}.$$

A central extension is through-focus correction. Instead of optimizing a single-focus objective, cuLitho uses an average over three foci $O_{EM}(f,o,p)$0:

$O_{EM}(f,o,p)$1

The paper states that this average is used together with context-aware tolerances to avoid conflicts such as bridging versus pinch. The solver employs a dynamic MEEF driver, identified as the local Jacobian $O_{EM}(f,o,p)$2, computed by finite-difference or adjoint methods.

The AI surrogate provides a warm start $O_{EM}(f,o,p)$3 and is reported to cut iterations by 2× while boosting end-to-end speed by 1.7×. Its loss is written as

$O_{EM}(f,o,p)$4

The integration of AI is therefore narrowly specified: it predicts near-final segment movements rather than replacing the lithographic simulator or the constrained optimizer. This is relevant to another potential misconception. The AI component is not described as generating curvilinear masks from scratch; rather, it operates on the Manhattan polygon layout and preserves MRC cleanliness without post-processing (Mukhopadhyay et al., 27 Jan 2026).

5. Reported acceleration, energy efficiency, and datacenter-scale implications

The reported average speedup over a production-grade CPU flow based on AMD Milan is 34×. When combined with the AI surrogate and without through-focus correction, the end-to-end speedup rises to 57×; with through-focus correction, the reported speedup is 24×. A representative component-level breakdown on NVIDIA H200 lists approximately 150× for diffractive optics modes, 34× for Booleans and edge intersections, 33–165× for spatial queries and MRC, 176× for contour extraction and measurement, and 1.7× from the AI surrogate through iteration-count reduction (Mukhopadhyay et al., 27 Jan 2026).

At the system level, the paper reports that sustaining a throughput of 30 layers per day would require replacing 40,690 CPU servers, occupying 1,403 racks and drawing 37.6 MW, with 353 H200 HGX nodes, occupying 118 racks and drawing 2.9 MW. The corresponding claimed reductions are 12× fewer racks, 13× lower energy consumption, 5.7× lower cost per layer, and a 12.9× reduction in $O_{EM}(f,o,p)$5 emissions over three years.

These numbers are presented as an argument that the significance of cuLitho is not confined to runtime reduction. The paper explicitly links the speedups to a reallocation of compute budget toward more rigorous lithographic solutions. A plausible implication is that performance headroom is treated as an enabling resource for higher-fidelity optimization, not solely as an efficiency metric.

6. Expanded lithographic scope, silicon validation, and stated assumptions

With the freed-up compute envelope, cuLitho is reported to reinvest a small fraction of GPU cycles into next-generation lithographic capabilities. The listed capabilities are curvilinear inverse lithography technology masks via true physics-based optimization without Manhattan constraints, high-NA EUV modeling with full 3D mask topography in the electromagnetic pipeline, and sub-angstrom or “subatomic” feature modeling through finer grids and rigorous EM kernels. The platform also includes variation-aware through-focus correction across $O_{EM}(f,o,p)$6, $O_{EM}(f,o,p)$7, and $O_{EM}(f,o,p)$8 while respecting MRC (Mukhopadhyay et al., 27 Jan 2026).

The conflict-resolution strategies explicitly named for through-focus optimization are hammer-head line ends, global retargeting of tip-to-tip by 1 nm, context-aware MEEF driver suppression on $O_{EM}(f,o,p)$9, power-line exception zones, and lateral segment movement restrictions for short lines. These details indicate that the expanded scope is coupled to rule-aware engineering constraints rather than to a purely unconstrained optimization.

The silicon validation was conducted at IMEC on chip-scale experiments involving 25 low-NA EUV designs with 28–36 nm pitch and random logic and SRAM content. Using a Hitachi GS1000 SEM for 7,350 images and 1.46 M CD measurements, the reported mask outcomes were a 35% wider process window, specified as depth-of-focus improving from approximately 60 nm to approximately 80 nm, and a 19% lower through-focus CD error, specified as improving from 3.7 nm to 3.0 nm. The paper further reports elimination of $$TCC(f_1,f_2;F)=\int S(o)\,P(f_1+o;F)\,P^*(f_2+o;F)\,do,$$0 pinches at $$TCC(f_1,f_2;F)=\int S(o)\,P(f_1+o;F)\,P^*(f_2+o;F)\,do,$$1 nm defocus and $$TCC(f_1,f_2;F)=\int S(o)\,P(f_1+o;F)\,P^*(f_2+o;F)\,do,$$2 bridges at $$TCC(f_1,f_2;F)=\int S(o)\,P(f_1+o;F)\,P^*(f_2+o;F)\,do,$$3 nm that affected CPU masks. Over 200 billion MRC checks and wafer contour analyses, all cuLitho masks are reported as clean and as meeting EPE targets with mean below 0.2 nm.

The paper also states its modeling assumptions. These include low-NA ($$TCC(f_1,f_2;F)=\int S(o)\,P(f_1+o;F)\,P^*(f_2+o;F)\,do,$$4) single-exposure EUV, bright-field masks without SRAFs, 28–36 nm pitches, calibrated resist blur kernels, and fixed thresholding. Boundary conditions for EM masks are stated to assume finite-difference or Fourier-modal truncation with sub-wavelength sampling. These assumptions are essential for interpreting the scope of the silicon results: the validation is quantitative and chip-scale, but it is not presented as covering every lithographic regime. This suggests that the claims about high-NA EUV and subatomic modeling are statements about enabled computational capability within the platform, whereas the experimentally quantified in-silicon results are reported for the low-NA conditions just listed.