NanoVSR: Edge-Optimized Video Super-Resolution

• NanoVSR is a lightweight video super-resolution model that employs a fully convolutional, bidirectional recurrent architecture to process low-resolution frames efficiently.
• It utilizes structural reparameterization to fuse multi-branch training blocks into a standard convolution, reducing runtime by up to 10–20× on edge hardware.
• The model achieves competitive restoration quality through implicit spatio-temporal alignment via progressive training, enabling real-time deployment on platforms like NVIDIA Jetson Orin NX.

Searching arXiv for the NanoVSR paper and a small set of directly related VSR baselines for accurate citation support. NanoVSR is a video super-resolution (VSR) model introduced as a scalable, fully convolutional architecture for resource-constrained edge devices, with an explicit emphasis on hardware friendliness for ONNX and TensorRT deployment and an avoidance of transformers, explicit optical flow, and custom CUDA operations (Pawlicki et al., 11 Jul 2026). It is described as a lightweight, bidirectional recurrent network built solely from standard convolutions and tensor operations, using structural reparameterization to collapse multi-branch training blocks into standard convolutions during inference, and relying on progressive training to learn spatio-temporal alignments implicitly rather than through explicit motion compensation (Pawlicki et al., 11 Jul 2026).

1. Architectural definition

NanoVSR is formulated for an input sequence of low-resolution frames $x \in \mathbb{R}^{T \times 3 \times H \times W}$ and is organized into shallow feature extraction, bidirectional recurrent temporal propagation, and fusion with upsampling (Pawlicki et al., 11 Jul 2026). Each input frame $x_i$ is first processed independently by a multi-branch extraction block: $$f_i = \mathcal{H}_{ext}(x_i), \quad \forall i \in \{1, \dots, T\}.$$

Temporal aggregation is then performed through forward and backward recurrent paths without explicit motion compensation: $$h^{\rightarrow}_i = \mathcal{H}_{forward}\left(f_i + h^{\rightarrow}_{i-1}\right), \quad h^{\leftarrow}_i = \mathcal{H}_{backward}\left(f_i + h^{\leftarrow}_{i+1}\right).$$

A central architectural choice is element-wise addition for context propagation, replacing standard channel concatenation. The paper states that this halves the memory bandwidth and reduces computational overhead (Pawlicki et al., 11 Jul 2026). After bidirectional propagation, the two hidden states are fused by channel-wise concatenation followed by a $1 \times 1$ convolution bottleneck: $$f^{fused}_i = \mathcal{H}_{fusion}\left([h^{\rightarrow}_i, h^{\leftarrow}_i]\right).$$

The fused representation is passed through cascading sub-pixel (PixelShuffle) modules with two $2\times$ upscales and PReLU activations, and a global bilinear upsampled residual is added to produce the high-resolution frame: $$\hat{y}_i = \mathcal{H}_{up}(f^{fused}_i) + \mathrm{Bilinear}_{\uparrow 4}(x_i).$$

This organization places NanoVSR within recurrent VSR design space while removing hardware-incompatible elements such as flow estimation and memory-intensive concatenations (Pawlicki et al., 11 Jul 2026). A plausible implication is that the model’s deployment profile is determined as much by operator choice as by parameter count.

2. Structural reparameterization and inference form

NanoVSR employs structural reparameterization, described as inspired by RepVGG, in order to maximize inference efficiency (Pawlicki et al., 11 Jul 2026). During training, each block is a multi-branch structure comprising a $3 \times 3$ convolution with BatchNorm, a $1 \times 1$ convolution with BatchNorm, and an identity shortcut with BatchNorm. During deployment, all branches, together with BN statistics, are mathematically fused into a single $x_i$0 convolution kernel and bias, yielding a single-branch structure at inference.

The stated benefits are operational rather than merely architectural. The paper attributes to this design the elimination of memory fragmentation, the conversion of every block into a single standard convolution, deep fusion and kernel launch efficiency on hardware like TensorRT, and full ONNX and TensorRT compatibility without custom CUDA ops (Pawlicki et al., 11 Jul 2026). In the paper’s ablations, omitting structural reparameterization by leaving multi-branch blocks unfused doubles the runtime, while training as a single-branch network hurts PSNR by approximately $x_i$1 dB (Pawlicki et al., 11 Jul 2026).

These results position structural reparameterization as a dual-purpose mechanism: a richer optimization topology during training and an unfragmented compute graph during inference. This suggests that NanoVSR’s efficiency claims depend not only on being “fully convolutional” in a generic sense, but specifically on the training–deployment asymmetry created by branch fusion.

3. Implicit spatio-temporal alignment

A defining feature of NanoVSR is the omission of explicit optical flow and deformable convolution mechanisms that are common in traditional VSR models (Pawlicki et al., 11 Jul 2026). Instead, temporal dependence is handled by bidirectional recurrence with additive propagation, where the hidden state is updated using the elementary sum with the features from each frame. The paper characterizes this as relying on the network’s learning capacity to extract useful temporal dependencies and implicitly “align” the spatio-temporal data.

The reported ablation results indicate the trade-off clearly. Adding explicit motion alignment with SPyNet boosts PSNR by approximately $x_i$2 dB, but inflates parameters by $x_i$3 and more than doubles runtime, which the paper states is contrary to NanoVSR’s hardware-efficiency goals (Pawlicki et al., 11 Jul 2026). The stated interpretation is that NanoVSR sacrifices only a moderate amount of PSNR compared to models that explicitly use optical flow, while providing orders-of-magnitude lower runtime and memory overhead.

A common misconception in this design space is that the absence of explicit motion compensation implies the absence of temporal alignment altogether. NanoVSR does not make that claim. Rather, it asserts that alignment is learned implicitly through recurrence and training strategy (Pawlicki et al., 11 Jul 2026). Another misconception is that standard operators alone are insufficient for competitive VSR; the reported REDS4 results are presented precisely to contest that assumption for compact architectures.

4. Progressive two-stage training

The training procedure is explicitly curriculum-like and consists of two phases designed to facilitate convergence when alignment is implicit and representations must emerge from scratch (Pawlicki et al., 11 Jul 2026). In Phase 1, the model is pre-trained on short 7-frame sequences from Vimeo-90K for 50,000 iterations, with the stated focus of learning spatial features and short-term temporal fusion. In Phase 2, training switches to long 30-frame sequences from the REDS dataset for 100,000 iterations, with the stated aim of forcing the model to leverage bidirectional recurrence for long-term dependencies.

Optimization uses the Charbonnier loss,

$x_i$4

with $x_i$5, together with the Adam optimizer and a cosine annealing learning-rate schedule from $x_i$6 to $x_i$7 (Pawlicki et al., 11 Jul 2026). Training is performed with AMP using BFloat16 for faster and more memory-efficient training. Data augmentation includes flips, rotations, time reversal, and CutBlur.

The significance of this procedure lies in how it substitutes for explicit motion modules. The paper directly links progressive training to the model’s ability to maintain competitive restoration quality despite lacking explicit motion compensation (Pawlicki et al., 11 Jul 2026). This suggests that, in NanoVSR, temporal competence is not isolated in a dedicated alignment subnetwork but is distributed across recurrent propagation and training curriculum.

5. Quantitative performance and scaling

NanoVSR is evaluated on REDS4 with several parameter budgets, and the results are framed as a trade-off between PSNR and computational efficiency (Pawlicki et al., 11 Jul 2026). The paper reports that NanoVSR-226k attains 28.23 dB PSNR with 1.91 ms runtime and 43.9 FPS on NVIDIA Jetson Orin NX 16GB, NanoVSR-644k attains 28.64 dB with 2.98 ms runtime and 27.2 FPS, and NanoVSR-1.7M attains 29.15 dB with 4.27 ms runtime and 19.6 FPS. Comparative entries include EDVR-M at 30.53 dB and 27.3 ms runtime, BasicVSR at 31.42 dB, 15.2 ms runtime, and 8.0 FPS, IconVSR at 31.67 dB and 28.9 ms runtime, and RVRT at 32.75 dB and 47.9 ms runtime (Pawlicki et al., 11 Jul 2026).

Variant or baseline	REDS4 / runtime	Orin NX 16GB FPS
NanoVSR-226k	28.23 dB / 1.91 ms	43.9
NanoVSR-644k	28.64 dB / 2.98 ms	27.2
NanoVSR-1.7M	29.15 dB / 4.27 ms	19.6
BasicVSR	31.42 dB / 15.2 ms	8.0

The paper highlights NanoVSR-644k as delivering 28.64 dB PSNR on REDS4 while offering 27.2 FPS for 180×320 inputs on Orin NX 16GB, and describes this as a strong trade-off for a compact architecture (Pawlicki et al., 11 Jul 2026). It also states that inference cost can be up to 10–20× faster than heavy transformer-based or alignment-heavy methods at similar PSNR, and that gain per parameter diminishes beyond 5M parameters (Pawlicki et al., 11 Jul 2026).

These numbers indicate that the model is not positioned as state of the art in restoration quality. The paper states explicitly that NanoVSR-226k is 3–4 dB below SOTA in the 31–32 dB range, that NanoVSR-644k is approximately 2.8 dB below SOTA, and that heavier models such as RVRT remain substantially more accurate on REDS4 (Pawlicki et al., 11 Jul 2026). The central claim is therefore not maximal PSNR, but a different Pareto point for compact, edge-oriented VSR.

6. Edge deployment, applications, and implications

NanoVSR is presented as an edge-oriented model through strict adherence to standard ops, the absence of custom CUDA code, and a single-conv inference architecture, with explicit ONNX and TensorRT compatibility (Pawlicki et al., 11 Jul 2026). The paper identifies memory access as the primary bottleneck on edge accelerators and argues that the use of addition instead of feature concatenation in recurrence, together with fusion of multi-branch blocks, reduces that bottleneck (Pawlicki et al., 11 Jul 2026).

On NVIDIA Jetson Orin NX (16GB, 25W), the paper reports 27.2 FPS for 180×320 input and almost 13 FPS for 270×480 input for NanoVSR-644k (Pawlicki et al., 11 Jul 2026). The broader scaling table gives 43.9 and 19.5 FPS for NanoVSR-226k, 27.2 and 12.8 FPS for NanoVSR-644k, 19.6 and 8.9 FPS for NanoVSR-1.7M, 8.7 and 3.8 FPS for NanoVSR-5.4M, and 8.0 and 3.5 FPS for BasicVSR at those two resolutions (Pawlicki et al., 11 Jul 2026). The paper further states that heavier models such as BasicVSR fail to meet real-time even at higher power/TDP.

The applications listed in the paper are media streaming, video conferencing, surveillance, legacy media restoration, and any application requiring on-device/image privacy, low-latency, or energy-efficient video enhancement (Pawlicki et al., 11 Jul 2026). The broader implications it identifies are that high-quality VSR becomes practical for cost- or power-constrained devices, that computation and energy cost are orders of magnitude lower than transformer-based methods, and that deployment does not require custom hardware or software beyond support for ONNX/TensorRT or standard convolutions (Pawlicki et al., 11 Jul 2026).

The paper also includes an ethical note: as with all super-resolution, outputs are enhancements rather than reconstructions of “real” missing content, and users must avoid overinterpretation in surveillance or forensics (Pawlicki et al., 11 Jul 2026). That caveat is especially important because the model’s practical value derives partly from making on-device enhancement more accessible; easier deployment broadens applicability, but does not alter the epistemic status of super-resolved detail.

7. Position within VSR research

NanoVSR is framed against a contemporary VSR landscape in which many methods rely on transformers, explicit optical flow estimation, or custom operations such as deformable convolutions, each of which introduces computational overhead or hardware-deployment friction (Pawlicki et al., 11 Jul 2026). Its stated contribution is to move the design target from peak restoration quality toward a deployable balance of accuracy, runtime, and compatibility on hardware accelerators.

Within that framing, the model’s principal technical identity combines four choices: a fully convolutional architecture, bidirectional recurrence, structural reparameterization, and progressive training (Pawlicki et al., 11 Jul 2026). The result is a system that, according to the paper, achieves real-time or near-real-time VSR on Jetson-class hardware while remaining competitive in restoration quality for compact architectures. The official code repository is provided at https://github.com/filippawlicki/nanovsr (Pawlicki et al., 11 Jul 2026).

A plausible implication is that NanoVSR exemplifies a broader methodological shift in efficient vision systems: replacing specialized alignment modules and fragmented operator graphs with standard-operator pipelines whose performance depends on training strategy and deployment-aware architecture. In that sense, NanoVSR is less a claim that explicit alignment is unnecessary in general than a demonstration that, under strict edge constraints, implicit alignment plus reparameterized convolution can define a viable VSR regime (Pawlicki et al., 11 Jul 2026).