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MLDES: Multilevel DES Architecture

Updated 7 December 2025
  • MLDES is a hierarchical modeling paradigm that leverages modular state/event structures to achieve scalable supervisory control in complex systems.
  • It employs aggregation, disaggregation, and event projection techniques to simplify control synthesis and ensure system-level consistency.
  • Bus-aware decomposition and layered supervisor synthesis drastically reduce computational complexity in large-scale systems like production lines.

A multilevel discrete-event system (MLDES) is an architectural and modeling paradigm for the modular analysis, synthesis, and supervisory control of complex hierarchical discrete-event systems (DES). MLDES architectures formally leverage hierarchical decomposition, projections, event aggregation, and coordination to enable tractable control and verification in large-scale and highly interdependent engineered systems. This approach has received focused development in the areas of multilevel supervisory control design, recursive bus-aware hierarchical synthesis, and system-level decision support in both traditional DES and extended finite automaton settings (Komenda et al., 2015, Baubekova et al., 30 Nov 2025, 0809.3688).

1. Formal Multilevel Structural Model

The structure of an MLDES is defined by a finite hierarchy of levels L={0,1,…,N}L = \{0,1,\ldots,N\}, with $0$ the lowest (finest granularity) and NN the top (coarsest aggregation). At each level ℓ∈L\ell \in L:

  • Sâ„“S_\ell: finite set of local states,
  • Eâ„“E_\ell: finite alphabet of local events (inputs), often partitioned into individual and global/coordinating events,
  • δℓ:Sℓ×Eℓ→Sâ„“\delta_\ell: S_\ell \times E_\ell \to S_\ell: deterministic local transition function.

The full multilevel system is MLDES=(L,{Sℓ,Eℓ,δℓ}ℓ∈L,{αℓ→ℓ+1},{ϕℓ+1→ℓ})MLDES = (L, \{S_\ell, E_\ell, \delta_\ell\}_{\ell \in L}, \{\alpha_{\ell \to \ell+1}\}, \{\phi_{\ell+1 \to \ell}\}) with two types of vertical inter-level connectors:

  • Aggregation αℓ→ℓ+1\alpha_{\ell \to \ell+1}: maps finite sequences over Eℓ∗E_\ell^* to Eâ„“+1E_{\ell+1}, encoding upward reporting of local event histories as coarser events.
  • Disaggregation ϕℓ+1→ℓ\phi_{\ell+1 \to \ell}: maps Eâ„“+1E_{\ell+1} to finite sequences over Eℓ∗E_\ell^*, distributing higher-level commands downward as low-level actions (0809.3688).

A global plant model can be represented as the synchronous product of nn subsystem generators,

G=∥i=1nGi,Gi=(Qi,Ai,fi,q0,i,Qm,i),G = \|_{i=1}^{n} G_i, \quad G_i=(Q_i, A_i, f_i, q_{0,i}, Q_{m,i}),

with global language L=∥i=1nL(Gi)L = \|_{i=1}^n L(G_i). Subsystems are organized into mm low-level groups (I1,…,Im)(I_1, \ldots, I_m), each supervised by a group coordinator GkjG_{k_j} and, at a higher level, a global coordinator GkG_k participates in the supervision of the group coordinators (Komenda et al., 2015).

2. Decomposition, Projections, and Bus Structures

Complexity reduction relies on coordinated decomposition via event projections and the systematic identification and management of shared-event components ("buses"). For each subsystem group IjI_j:

  • AIj=∪i∈IjAiA_{I_j} = \cup_{i \in I_j} A_i: alphabet union of subsystem group,
  • AkjA_{k_j}: group coordinator alphabet (union of pairwise shared events in IjI_j),
  • AkA_k: high-level coordinator alphabet (union of shared events across groups).

Projections such as Pi+kj:A∗→(Ai∪Akj)∗P_{i+k_j}:A^* \to (A_i \cup A_{k_j})^* and Pk:A∗→Ak∗P_{k}:A^* \to A_k^* establish coordinated viewpoints for modular control synthesis and verification.

MLDES with bus-aware decomposition utilizes dependency structure matrices (DSM) to formalize plant and requirement interdependencies. A DSM enables Markov-clustering-based detection of bus components—subsystems with high degree (number of shared dependencies above a threshold θ\theta)—which are systematically assigned to branches in the hierarchy to minimize entangled synthesis subproblems (Baubekova et al., 30 Nov 2025).

Artifact/Notion Role in MLDES Formalism/Usage
Aggregation α\alpha Upward event reporting Eℓ∗→Eℓ+1E_\ell^* \to E_{\ell+1}
Disaggregation ϕ\phi Downward control action Eℓ+1→Eℓ∗E_{\ell+1} \to E_\ell^*
Bus High-connectivity component d(i)=∑b≠iP(i,b)>θd(i) = \sum_{b \neq i} P(i,b) > \theta
Projection PP Modular state/event mapping A∗→(A′′)∗A^* \to (A'')^*

3. Supervisory Control Synthesis Procedures

Top-Down Approach

In the top-down methodology, high-level decomposition is first performed by augmenting the alphabets of coordinators to ensure that the specification KK is conditionally decomposable:

K=∥j=1mPIj+k(K),PIj+k(K)=∥i∈IjPi+kj(K).K = \|_{j=1}^m P_{I_j + k}(K), \quad P_{I_j + k}(K) = \|_{i \in I_j} P_{i + k_j}(K).

Coordinators are synthesized recursively: for each group, AkjA_{k_j} is extended to cover all internally shared events and the group coordinator GkjG_{k_j} is constructed as ∥i∈IjPkj(Gi)\|_{i \in I_j} P_{k_j}(G_i). Supervisory controllers are then synthesized under three-level conditional controllability and, if applicable, conditional normality conditions, ensuring a maximally permissive and nonblocking solution using only local controllers (Komenda et al., 2015).

Bottom-Up and Combined Procedures

When KK fails conditional decomposability or controllability, bottom-up, a posteriori supervisors are computed recursively. Local supremal conditionally normal (supCN) supervisors are synthesized at the lowest level, then aggregated upwards through intersection and further supCN synthesis, yielding a set of layer-specific and global a posteriori supervisors. For prefix-closed KK, this approach guarantees that maximal permissiveness is restored, i.e., the a posteriori supervisors implement exactly the supremal achievable sublanguage under multilevel constraints (Komenda et al., 2015).

The combined top-down/bottom-up approach incorporates hierarchical decomposition, local and group supervisor synthesis, coordinator extension for nonblockingness, and a structured process for computing a hierarchy of supCN supervisors and a posteriori conflict resolution.

Bus-Aware Tree-Structured Synthesis

For large-scale plants, a recursive procedure builds a tree of local synthesis subproblems by traversing DSM-based clusters and their detected bus/non-bus partitions. The recursive tree "Transform" operation assigns to each node a local plant and requirement set, ensures each requirement is uniquely attributed, and that all plant components appear in at least one leaf. Supervisor synthesis is then performed locally at each node; the global supervisor is their synchronous product. Empirically, this leads to a dramatic reduction in the sum of local controlled state-space sizes compared to a monolithic approach, e.g., in the Festo production line example, a reduction by a factor of >6.7>6.7 (Baubekova et al., 30 Nov 2025).

4. Hierarchical Information System and Control Loop

Bagdasaryan’s architecture integrates MLDES within a multi-layer information system supporting real-time monitoring, scenario generation, simulation, and decision analysis (0809.3688):

  • Monitoring Database: Time-series of events, alarms, logs,
  • Parameters Library: Hierarchical parameter definitions and classifiers,
  • Canonical Model Builder: Graphical/state-transition diagram construction for each level,
  • Monitoring-Data Interpreter: Online state recognition, transition counting,
  • Scenario Generator: IF–THEN rules for control-intervention generation and interactive scenario editing,
  • Visualization & Simulation: Dashboards, what-if simulators applying sequences of control interventions via Ï•\phi and aggregating their high-level outcomes via α\alpha.

A global Mealy automaton controller CC operates in the control loop, emitting events to levels based on full-system state and (optionally) recent event histories; feedback and aggregation propagate information and control actions vertically across the hierarchy.

Pseudocode for one simulation cycle involves sampling state across levels, controller decision, event execution, event aggregation upward, and optional disaggregation of new controls downward.

5. Key Theorems and Complexity Insights

Several compositionality and correctness results underlie MLDES synthesis:

  • Local-to-Global Consistency: If each lower-level diagram is consistent and aggregation maps preserve state order, then the composed higher-level diagram is consistent and globally reachable.
  • Scenario Composability: If two scenarios differ only below some level kk, their evolution and outcomes above kk agree, formalizing hierarchical independence.
  • Supremality Preservation: For prefix-closed KK, the a posteriori supervisors in bottom-up synthesis do not reduce maximal permissiveness; that is, the constructed local and coordinator supervisors together realize the supremal three-level conditionally controllable and normal sublanguage (Komenda et al., 2015).
  • Complexity: Under observer conditions for projections, all supCN and coordinator computations are polynomial in the combined subsystem state-sizes and alphabet sizes; bus-aware clustering uniformly balances computational effort and limits individual subproblem state-space blow-up (Komenda et al., 2015, Baubekova et al., 30 Nov 2025).

6. Illustrative Case Studies

Two-Machine System

Consider G1G_1 and G2G_2 with alphabets {a,x}\{a,x\} and {b,x}\{b,x\} (shared xx). Specification KK requires every aa to be followed by bb before any next aa. With a single group, decomposed projections and local supCN controllers enforce controllability and normality on xx, enabling aa and bb only when both machines agree on the shared event, consistent with modular and maximally permissive distributed synthesis (Komenda et al., 2015).

Festo Production Line

For a large-scale plant of >1025>10^{25} states, monolithic synthesis is computationally intractable. DSM-guided MLDES without bus separation requires 24 supervisors and 50,638 aggregate states. Introducing global and local bus-aware decomposition at each level increases the number of local supervisors to 50 but reduces the maximal subproblem size below 10410^4 and the total state-space to $7,393$—a factor >6.7>6.7 reduction—by redistributing high-connectivity (bus) components lower in the hierarchy (Baubekova et al., 30 Nov 2025).


The MLDES architecture thus formalizes hierarchical decomposition, vertical event aggregation/disaggregation, conditionally decomposable control synthesis, and information-system integration. It enables scalable, rigorously correct, and maximally permissive supervisory control for large-scale, highly interconnected discrete-event systems, as established in the foundational works of Bagdasaryan (0809.3688), van Schuppen, Lomuscio, and Baubekova et al. (Komenda et al., 2015, Baubekova et al., 30 Nov 2025).

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