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MixCache: Hybrid Caching for Video Diffusion

Updated 4 July 2026
  • MixCache is a hybrid caching framework that reuses step-level, CFG-level, and block-level computations to accelerate video diffusion transformer inference.
  • It profiles the DiT model offline and triggers caching dynamically based on relative L1 distance metrics, ensuring efficient runtime decisions.
  • Empirical evaluations on Wan 14B, HunyuanVideo, and CogVideoX demonstrate significant latency reductions with minimal impact on generation quality.

Searching arXiv for the primary MixCache paper and closely related caching methods in diffusion/video DiT inference. MixCache is a hybrid, training-free caching framework for efficient video diffusion transformer inference that accelerates sampling by mixing step-level, classifier-free-guidance-level, and block-level cache reuse over the diffusion trajectory rather than committing to a single caching strategy. It profiles a given video DiT once offline and then, at runtime, decides per timestep both when caching should be enabled and which cache granularity should be used, with reported results on Wan 14B, HunyuanVideo, and CogVideoX showing substantial latency reduction while maintaining generation quality (Wei et al., 18 Aug 2025).

1. Problem setting and motivation

Video diffusion transformers combine a diffusion process with a Transformer backbone. Sampling runs a reverse process from Gaussian noise xTx_T to a clean video x0x_0 over TT denoising steps, and each step invokes a large stack of DiT blocks, often with classifier-free guidance, which doubles the number of forward passes per step through one conditional and one unconditional branch. The formulation given for the forward process, the DiT denoiser, the reverse step, and CFG is

xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]

ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)

xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]

ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).

This inference path is computationally expensive because each denoising step is large, high-resolution, long-video generation requires many such steps, and CFG adds another branch. The paper notes that generating a single 5-second 720p video with a large DiT on one GPU can take approximately 50 minutes (Wei et al., 18 Aug 2025).

The immediate context for MixCache is the broader literature on inference-time acceleration for diffusion models. The data identify three major families: fewer steps or better solvers, distillation, and caching. Fewer-step solvers such as DDIM, DPM-Solver, and DPM-Solver++ reduce the number of sampling steps but can reduce quality, particularly for video where temporal consistency is delicate. Distillation reduces steps by training a student model, but requires expensive retraining and model-specific tuning. Caching instead reuses previously computed outputs or features when the diffusion process exhibits redundancy. MixCache targets the limitations of prior caching approaches, which typically choose one granularity and apply it more or less uniformly, producing a rigid speed-quality trade-off (Wei et al., 18 Aug 2025).

2. Redundancy model and cache granularities

The framework is based on the observation that video DiT inference contains three principal forms of redundancy: step-level redundancy across adjacent timesteps, CFG-level redundancy between conditional and unconditional branches at the same timestep, and block-level redundancy across corresponding transformer block activations at adjacent timesteps. These are measured by relative L1L_1 distances:

Dtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}

Dtcfg=OtuncondOtcond1Otcond1D^{cfg}_t = \frac{\|O^{uncond}_t - O^{cond}_t\|_1}{\|O^{cond}_t\|_1}

x0x_00

Small values of x0x_01 indicate high similarity and therefore high reuse potential. The central empirical claim is that these redundancies are dynamic: they vary over timesteps, prompts, and models, and each granularity decays differently over time. This is the basis for the paper’s argument that a single fixed caching strategy is inherently suboptimal (Wei et al., 18 Aug 2025).

Granularity Reuse rule Characteristic effect
Step-level x0x_02 Coarsest; skips the full DiT forward
CFG-level Reuse one branch via cached x0x_03 Mid-level; skips one branch’s compute
Block-level Reuse x0x_04 and run blocks x0x_05 Finer; skips part of the network

Step-level caching reuses the entire DiT output from timestep x0x_06 for timestep x0x_07. It offers the maximum speed benefit because it skips the full DiT forward, but it also carries the greatest trajectory risk when the latent state has materially changed. CFG-level caching computes the conditional branch normally, approximates the unconditional branch as x0x_08, and then applies CFG. Its practical attraction is that it roughly halves the number of DiT forward passes per step, but its quality cost depends on the reliability of the cached guidance correction. Block-level caching reuses activations at a chosen block index x0x_09 across adjacent steps by feeding the cached output of block TT0 at step TT1 into block TT2 at step TT3 and then running the remaining blocks normally, including CFG computations. It yields more moderate speedup but more controllable error (Wei et al., 18 Aug 2025).

MixCache explicitly restricts itself to these three granularities rather than token-level caching. The stated reasons are that token-level caching requires heavy modifications to attention and token scoring, is more fine-grained, yields smaller speedups, and adds overhead (Wei et al., 18 Aug 2025).

3. Context-aware triggering and adaptive hybrid selection

The core design consists of two interacting mechanisms: a context-aware cache triggering strategy that determines when caching should begin and an adaptive hybrid cache decision strategy that determines which granularity should be used at each cache-enabled step (Wei et al., 18 Aug 2025).

The triggering mechanism starts with a warm-up phase in which there is no caching and every step is fully computed. The reason is that early steps are described as highly sensitive to perturbations and exhibit low redundancy, reflected in large TT4. Caching remains disabled while TT5, where TT6 is an offline-profiled threshold. Once TT7 drops below TT8, inference enters the cache-enabled phase.

Within the cache-enabled phase, MixCache still performs periodic full-compute steps in order to limit error accumulation. The paper defines a cache interval TT9, with two discrete interval sets: an accuracy-prior regime with xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]0 and an efficiency-prior regime with xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]1. A counter cnt is maintained modulo xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]2; when cnt == 0, the framework performs full computation, and otherwise it performs a cached computation. After each full-compute step, xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]3 is adjusted using the relative xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]4 distance xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]5 between consecutive full-compute outputs. In the accuracy-prior regime,

xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]6

with an analogous larger-interval rule for xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]7. The intended behavior is that small drift leads to larger xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]8 and less frequent full recomputation, while larger drift forces more conservative scheduling (Wei et al., 18 Aug 2025).

The hybrid selection mechanism scores each candidate cache mode by combining a similarity term and an impact term. For xt=δtxt1+1δtϵt,t[1,T]x_t = \sqrt{\delta_t} x_{t-1} + \sqrt{1 - \delta_t}\,\epsilon_t,\quad t \in [1,T]9, the framework defines

ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)0

and chooses the cache mode greedily by

ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)1

The impact indicators are derived offline. For each granularity, the method estimates the mean ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)2 and standard deviation ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)3 of the cache-induced difference tensor over many prompts and timesteps, defines global ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)4 and ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)5, injects Gaussian noise with those statistics, and measures how much the final video deviates from the original. This deviation is the impact indicator ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)6. The reported empirical result is that step-level and CFG-level impacts become approximately constant after warm-up, while block-level impact depends on both timestep and block index. CFG-level impact is reported to be much higher than the others, and the paper states that its perturbation can be an order of magnitude stronger than step- or block-level interference for the same noise statistics (Wei et al., 18 Aug 2025).

At runtime, MixCache computes ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)7, ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)8, and ϵθ(xt)=fL1fL2f0(xt)\epsilon_\theta(x_t) = f_{L-1} \circ f_{L-2} \circ \cdots \circ f_0(x_t)9 using relative xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]0 norms, with candidate block indices xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]1 to avoid large memory cost. It then evaluates xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]2, xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]3, and xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]4 and selects the minimum. To avoid degenerate behavior in which one mode dominates indefinitely, the framework multiplies the previously used mode’s score by a penalty at the next step; in the reported experiments this penalty is set to 5 (Wei et al., 18 Aug 2025).

4. Operational procedure and implementation

Operationally, MixCache is a training-free and model-agnostic inference wrapper over video DiT architectures. It assumes a DiT-style transformer with identifiable blocks xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]5, access to both conditional and unconditional branches for CFG, and the ability to intercept and reuse intermediate block outputs (Wei et al., 18 Aug 2025).

The paper’s simplified procedure has two phases. The offline profiling phase determines xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]6, xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]7, xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]8, and the impact values xt1=Φ(xt,t,ϵθ(xt)),t[T,1]x_{t-1} = \Phi(x_t, t, \epsilon_\theta(x_t)),\quad t \in [T,1]9, ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).0, and ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).1. The runtime phase iterates over timesteps, computes the similarity metrics, decides whether the process is still in warm-up, and if not, alternates between periodic full recomputation and cache-enabled execution. Within a cached step, the actual reuse rule depends on the currently selected mode: direct output reuse for step-level caching, one-branch reuse for CFG-level caching, or truncated-network execution for block-level caching (Wei et al., 18 Aug 2025).

In implementation terms, the framework adds hooks around the DiT forward pass to store ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).2 and candidate block outputs ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).3, compute the relative ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).4 distances, and invoke the appropriate cache mode. The sampling loop maintains warm-up state, the cache interval ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).5, the current cache mode, and the relevant counters. The stated memory overhead is the storage of a small subset of block activations, such as blocks 10, 20, and 30, and this subset is intentionally short to avoid out-of-memory conditions. The framework is reported to work on Wan 14B, HunyuanVideo, and CogVideoX without structural changes. It is also described as compatible with multi-GPU parallelism such as Ulysses, where only the cache mode decisions require synchronization, and that synchronization cost is characterized as small (Wei et al., 18 Aug 2025).

A plausible implication is that MixCache functions as a controller over existing reuse primitives rather than as a new low-level cache primitive. That interpretation follows from the repeated characterization of the method as a thin, training-free framework that integrates step-, CFG-, and block-level strategies without modifying model structure (Wei et al., 18 Aug 2025).

5. Empirical evaluation and ablation results

The evaluation covers Wan 2.1 14B at 832×480 and 1280×720, HunyuanVideo at 960×544, and CogVideoX 5B at 820×480, all with ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).6 in the reported settings. Baselines are all caching-based and training-free: TeaCache, FasterCache, BlockDance, and PAB. Quality is assessed with VBench, LPIPS, PSNR, and SSIM; efficiency is assessed with latency per prompt and speedup relative to uncached inference. The experiments use approximately 4720 videos per configuration across 64 A800 GPUs and are reported to have taken approximately one month (Wei et al., 18 Aug 2025).

Setting Original latency MixCache result
Wan 14B, 480p, 5s, ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).7 900 s 465 s with 1.94× speedup
Wan 14B, 720p, 5s, ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).8 3168 s 1742 s with 1.82× speedup
HunyuanVideo, 540p, 5s, ϵ~θ(xt,t,c)=(1+g)ϵθ(xt,t,c)gϵθ(xt,t,ϕ).\tilde{\epsilon}_\theta(x_t,t,c) = (1+g)\cdot\epsilon_\theta(x_t,t,c) - g\cdot\epsilon_\theta(x_t,t,\phi).9 2289 s 1151 s with 1.97× speedup
CogVideoX 5B, 480p, 6s, L1L_10 443 s 256 s with 1.73× speedup

For Wan 14B at 480p, the original system has VBench 84.05 and latency 900 s. TeaCacheL1L_11 reports VBench 83.95, LPIPS 0.244, PSNR 18.60, SSIM 0.688, latency 612 s, and 1.47× speedup. FasterCache reports VBench 83.40, LPIPS 0.140, PSNR 23.26, SSIM 0.796, latency 633 s, and 1.42× speedup. BlockDanceL1L_12 reports VBench 83.48, LPIPS 0.129, PSNR 24.01, SSIM 0.811, latency 679 s, and 1.29× speedup. PABL1L_13 reports VBench 83.00, LPIPS 0.166, PSNR 22.29, SSIM 0.772, latency 717 s, and 1.25× speedup. By comparison, MixCacheL1L_14 reports VBench 83.97, LPIPS 0.124, PSNR 23.45, SSIM 0.814, latency 528 s, and 1.70× speedup, while MixCacheL1L_15 reports VBench 83.90, LPIPS 0.132, PSNR 22.94, SSIM 0.804, latency 465 s, and 1.94× speedup (Wei et al., 18 Aug 2025).

The 720p Wan 14B result is reported as latency 3168 s for the original system and 1742 s for MixCacheL1L_16, with VBench essentially unchanged at 83.70 versus 83.66. For HunyuanVideo at 540p, MixCacheL1L_17 reports VBench 80.98 versus 81.13 original, LPIPS 0.060, PSNR 26.86, SSIM 0.906, latency 1151 s, and 1.97× speedup. For CogVideoX 5B at 480p, MixCacheL1L_18 reports VBench 80.15 versus 80.89 original, LPIPS 0.160, PSNR 26.86, SSIM 0.880, latency 256 s, and 1.73× speedup (Wei et al., 18 Aug 2025).

The paper also reports ablations on Wan 14B 480p. A hybrid strategy with fixed L1L_19 but no adaptive Dtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}0-scaling yields LPIPS 0.082, PSNR 25.74, SSIM 0.854, latency 593 s, and 1.51× speedup. Step-only with Dtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}1 yields LPIPS 0.147, PSNR 22.25, SSIM 0.775, latency 545 s, and 1.65× speedup. CFG-only with Dtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}2 yields LPIPS 0.080, PSNR 25.90, SSIM 0.853, latency 623 s, and 1.44× speedup. Block-only with Dtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}3 yields LPIPS 0.114, PSNR 24.62, SSIM 0.809, latency 537 s, and 1.67× speedup. MixCacheDtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}4 yields LPIPS 0.079, PSNR 25.91, SSIM 0.858, latency 465 s, and 1.94× speedup. The paper interprets these results as evidence that adaptive Dtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}5-scaling improves both quality and speed over fixed intervals and that hybrid cache choice dominates single-granularity regimes (Wei et al., 18 Aug 2025).

Qualitatively, the reported visual comparisons state that MixCache videos are nearly indistinguishable from the original, preserve subject shapes, motion, and background consistency, and avoid the flickering or temporal artifacts that can emerge under aggressive caching (Wei et al., 18 Aug 2025).

Within the video DiT caching literature, MixCache is positioned against single-granularity methods such as step-level TeaCache, CFG- and block-oriented FasterCache, and fixed block-reuse methods such as BlockDance and PAB. Its distinctive claim is not the invention of a new primitive cache type but the adaptive mixing of existing granularities on a per-timestep basis. The paper’s interference analysis is central to this distinction: no single granularity dominates across all steps, CFG-level interference is substantially larger, block-level interference is time-dependent, and step-level interference is relatively stable after warm-up. This suggests that the main conceptual contribution is a scheduling and arbitration layer over heterogeneous cache modes rather than a replacement for them (Wei et al., 18 Aug 2025).

A useful comparison is with OmniCache, another training-free DiT acceleration method that adopts a trajectory-oriented global perspective on cache reuse. OmniCache emphasizes global sampling geometry, low-curvature reuse regions, and explicit cache-induced noise correction, whereas MixCache emphasizes per-timestep arbitration among step-, CFG-, and block-level caches using similarity and impact indicators. The data explicitly note that OmniCache does not mention a method named MixCache and that any comparison is conceptual rather than direct (Chu et al., 22 Aug 2025).

The term “MixCache” also has an unrelated use in large-scale CTR training. In “ScaleFreeCTR: MixCache-based Distributed Training System for CTR Models with Huge Embedding Table,” MixCache denotes a CPU-GPU embedding cache mechanism for sparse recommendation models, with a manager in CPU memory and buffers in GPU HBM. That system addresses host-GPU transfer latency and embedding synchronization for massive tables, not inference acceleration in diffusion transformers. The name overlap is therefore terminological rather than technical (Guo et al., 2021).

The explicit limitations of the video DiT MixCache framework are threefold. First, each base model requires offline profiling to determine Dtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}6, Dtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}7, Dtstep=OtstepOt1step1Ot1step1D^{step}_t = \frac{\|O^{step}_t - O^{step}_{t-1}\|_1}{\|O^{step}_{t-1}\|_1}8, and impact curves, described as a one-time cost that still requires running approximately 100 prompts. Second, the decision rule and penalty are heuristic rather than learned, and the paper states that there is no guarantee of global optimality. Third, although the framework uses CFG-level caching, the paper’s own interference analysis shows that it can be heavily distorting if overused, so the impact term must keep it under control. The scope is also limited to video DiTs; applicability to image diffusion and other modalities is presented only as a future direction (Wei et al., 18 Aug 2025).

A plausible implication is that subsequent work may combine MixCache’s hybrid-granularity controller with trajectory-aware scheduling or richer error models of the kind emphasized by OmniCache. The data support that implication only indirectly: MixCache isolates granularity-specific interference and performs online arbitration, while OmniCache treats cache error as trajectory perturbation and distributes reuse globally (Chu et al., 22 Aug 2025).

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