Memory-Resilient Codes

Updated 17 December 2025

Memory-resilient codes are coding schemes designed to tolerate transient faults, partial defects, and wear limitations in modern memory devices.
They employ methodologies such as expander-LDPC architectures, iterative decoding, and masking techniques to optimize redundancy and fault tolerance.
These codes enable reliable operation across diverse platforms like DRAM, Flash, and resistive memories by balancing trade-offs between rate, endurance, and error correction.

Memory-resilient codes are classes of coding schemes and architectural protocols designed to ensure robust data storage and retrieval in the presence of transient faults, partial cell defects, non-uniform cell reliability, and hardware-induced constraints in modern and emerging memory technologies. Their deployment is critical for enabling reliable operation across volatile and non-volatile platforms such as DRAM, Flash (MLC/TLC/QLC/PLC), resistive memories (PCM, RRAM), and future scalable memory architectures. The technical landscape encompasses expander-LDPC and iterative decoding, reconfigurable constrained codes, stuck-at and partial-defect masking, rewriting and endurance-limited codes, and hybrid pillars such as low-overhead erasure/redundancy protocols. This article organizes the foundational models, major constructions, analytical bounds, operational regimes, and key trade-offs across recent arXiv literature.

1. Fault Models and Coding-Theoretic Frameworks

Modern memory-resilient codes are designed under explicit error and defect models suited to the underlying physical substrate:

Transient Fault and Adversarial Models: In volatile memories, faults may affect storage elements, logic gates, and decoders at every correction instant, bounded by fractions $\alpha_m$ (memory cells), $\alpha_+$ (2-input XOR gates), and $\alpha_\gamma$ ( $\gamma$ -input majority gates). Transient faults occur in worst-case (adversarial) patterns, requiring per-step remediation below a global threshold (0705.0044).
Partial-Defect Models: Non-volatile memories experience permanent and partial defects—cells that can only store values above a stuck-at threshold $s$ , or, dually, cannot exceed an $s$ value. The encoder typically knows defective coordinates and stuck levels, but the decoder may lack such information (Wachter-Zeh et al., 2015, Kim et al., 2022).
Rewrite- and Wear-Limited Models: Flash and resistive memories possess cells that tolerate only a limited number $\ell$ of changes. In endurance-limited regimes, global codes must minimize the total programming events per cell—each cell is “stuck” after $\ell$ writes (Chee et al., 2021, Yaakobi et al., 2012, Burshtein et al., 2012).
Non-Stationary and Asymmetric Channel Models: Physical features such as wire resistance, sneak path, and inter-cell interference (ICI) induce spatially variant error probabilities, requiring channels to be modeled as per-cell BSCs/BACs or channel constraints that forbid certain local patterns (Zorgui et al., 2019, Hareedy et al., 2020, Kobovich et al., 2022).

The coding-theoretic objectives involve:

Error correction under unknown and time-varying error locations,
Defect/constraint masking where read/write constraints must always be satisfied,
Minimization of redundancy (extra symbols or bits beyond information payload),
Efficient encoding/decoding within hardware constraints (e.g., bounded gate complexity, $O(N\log N)$ time).

2. Expander-Based Reliable LDPC Architectures

The foundational architecture for memory resilience under transient faults is based on expander graphs and LDPC codes (0705.0044):

Tanner Graph Expansion: A $(n, \gamma, \rho)$ -regular LDPC code is associated with a bipartite graph whose one-step neighborhood growth property ensures robust message propagation. For a small error set $S$ of variables, the neighborhood in the check side expands by a factor $(3/4+\epsilon)\gamma$ .
Iterative Decoding and Correction: Each correction cycle implements Gallager B / parallel bit-flipping, where messages are exchanged over the graph and majority logic applied per variable.
Fault-tolerance Guarantees: The system provably corrects any set of errors or faults up to an expansion threshold $\alpha n$ as long as

$\alpha_m + \gamma(\rho - 2)\alpha_+ + \alpha_\gamma < \alpha(1 + 4\epsilon)(4\epsilon)/2$

No failure occurs outside the decodable region with probability at most $L \exp(-\Omega(n))$ under the independent error model.

Redundancy Trade-off: Redundancy is quantified via component count and code rate:

$R \leq \frac{1 + D_\gamma + \gamma(\rho-2)}{1 - \gamma/\rho}$

The expander-LDPC scheme attains a factor- $\gamma$ reduction compared to Taylor-Kuznetsov codes.

Numerical Optimization: Optimal trade-off occurs near $\rho \approx 2\gamma, r \approx 1/2$ , balancing rate, redundancy, and fault budget.

3. Masking and Correcting Partial Defects

Defect masking codes address the constraint that some memory cells (or portions of cells in MLC/QLC) are stuck at specific levels (Wachter-Zeh et al., 2015, Kim et al., 2022):

Explicit Constructions:
- Add-One-Scalar (Construction I): For $u < q$ defects, one scalar addition suffices (redundancy = $1$ symbol, asymptotically optimal if $u+1 | q$ ).
- Row Echelon (Construction II): For $u \geq q$ defects, codes using systematic matrices enable efficient masking with $r = n-k$ redundancy. Block-triangular forms guarantee that linear systems are solvable across arbitrary defect configurations.
- Reduction to Binary Stuck-at (Construction III): Arbitrary $u$ —convert the problem to binary masking and use known codes.
Generalizations: All constructions generalize to arbitrary stuck levels $s_i$ ; the same algorithms address cells unable to reach high levels (the dual model).
Capacity Bounds: For independent defects (fraction $p$ ), capacity is

$C_q(p,s) = 1 - p \log_q \left( \frac{q}{q-s} \right)$

Explicit constructions approach this capacity up to small additive factors for large $q$ or small $p$ .

Error + Masking Correction: Codes with minimum distance $d \geq 2(u+t)+1$ mask $u$ defective positions and correct up to $t$ random errors simultaneously (Kim et al., 2022). BCH and Reed–Solomon codes provide practical instantiations.

4. Endurance, Rewriting, and Locally Updatable Codes

In memories prone to wear (Flash, PCM, RRAM), codes must maximize rewritability and minimize cell-programming events (Yaakobi et al., 2012, Burshtein et al., 2012, Chee et al., 2021, Kim et al., 2016):

Flash Codes and Write Deficiency: Write deficiency $\delta(C) = n(q-1) - t$ quantifies wasted cell-level transitions. Stage-wise constructions (index-less / stacked binary indexing) achieve $\delta(C) = O(qk \log k)$ for $q \geq \log_2 k$ , otherwise $O(k \log^2 k)$ .
Locally Rewritable Codes: LWCs (inspired by locally repairable codes) guarantee that updating one information bit requires rewriting only $r^\star$ extra cells. The Singleton-type tradeoff is

$d^\star \leq n - k - \left\lceil \frac{k}{r^\star} \right\rceil + 2$

Small locality $r^\star$ improves endurance and power.

Endurance-limited Codes and Capacity: For $\ell$ -change $t$ -write ELM codes, the maximum per-cell sum-rate is $\log \sum_{i=0}^\ell {t \choose i}$ when the encoder is fully informed. Practical codes approach this bound by leveraging non-binary WOM codes.

5. Channel Constraints, Asymmetric and Reconfigurable Coding

Constraints induced by device physics (e.g. ICI, sneak-path, periodicity) demand codes that avoid harmful local patterns (Hareedy et al., 2020, Zorgui et al., 2019, Kobovich et al., 2022):

QA-LOCO Codes for Flash: $q$ -ary lexicographically ordered constrained codes forbid runs of $(q-1)$ separated by up to $x$ lower levels, suppressing ICI. Coding rate approaches $R(m,x) \geq 0.95 \log_2 q$ for $q \geq 4$ . Codes are reconfigurable by updating lookup tables as device conditions evolve (Hareedy et al., 2020).
Non-Stationary Polar Codes: In resistive crossbars, polar codes can be synthesized for per-cell BSC/BAC reliabilities, ordering bit-channels via sorted reliability and bit-reversal to minimize empirical BER. Code puncturing increases the HRS fraction, reducing sneak-current errors further with minor rate penalties (Zorgui et al., 2019).
Constrained Periodicity in Racetrack Memory: Efficient average-linear-time codes are constructed to avoid forbidden periodic patterns in windows of length $L$ , with one-symbol redundancy approaching the theoretical lower bound for sufficiently large $L$ (Kobovich et al., 2022).

6. Erasure and Residue Codes for High Availability

For remote/disaggregated memory architectures, memory-resilient codes include low-overhead erasure codes and systematic residue codes (Lee et al., 2019, Manzhosov et al., 2021):

Hydra (Erasure Coding for Remote Memory): Implements $(n,k)$ Reed–Solomon across slabs, with asynchronous parity generation and fast RDMA transport. Memory overhead is $1 + r/k$ (e.g. 1.25× for $(10,8)$ ), outperforming replication (2×) and providing superior latencies (5–7 µs median) and resilience to correlated failures via CodingSets group placement (Lee et al., 2019).
Residue Codes for DRAM ECC (MUSE ECC): Adapts classical residue codes for storage, offering ChipKill protection with 25–30% fewer check bits than Reed–Solomon, enabling in-line security metadata (memory tagging, Rowhammer defense) with negligible performance loss (Manzhosov et al., 2021).

7. Near-Capacity Strong Stuck-At Codes

The strong stuck-at model generalizes stuck-at coding by requiring correct decoding when the decoder does not know the defect fraction or positions. Fully explicit codes have been constructed that attain rates $R_N(\rho) \geq 1-\rho-\epsilon$ for any desired $\epsilon>0$ , and can be made deterministic or randomized; encoding/decoding is near-linear in length (Con et al., 27 Mar 2024). These codes solve the universal masking/decoding problem for unknown defect sets and apply directly to versatile encoding schemes in modern memory technologies.