Memory Base: Systems-Level Abstraction

• Memory Base is a persistent substrate that couples stored state with explicit update and access rules for ongoing computation.
• It is applied in domains like few-shot segmentation, knowledge base completion, and model editing to anchor performance and generalization.
• Systems leverage Memory Bases for GPU safety, FPGA emulation, and superconducting memory, balancing capacity, precision, and retrieval trade-offs.

“Memory Base” denotes a persistent substrate that stores and exposes structured state for later computation. In the cited literature, the term is used for learnable feature memories in few-shot segmentation, superposed neighborhood representations in knowledge base completion, explicit edit stores for model editing, event–entity stores for stateful LLM applications, per-allocation metadata for GPU memory safety, tunable memory-region state for system software emulation, and physically encoded device state in superconducting memory (Chen et al., 2024, Lalisse et al., 2021, Mitchell et al., 2022, Fu et al., 28 May 2026, Ziad et al., 25 Feb 2025, Hirofuchi et al., 2023, Kalashnikov et al., 2023). Across these uses, a memory base is not merely storage: it couples representation, update rules, and access semantics, and its behavior is defined as much by retrieval, reconstruction, or verification procedures as by what is stored.

1. Conceptual scope and recurrent structure

The cited works use “memory base” for several technically distinct objects, but they recur around a common triad: a stored state, a rule for updating that state, and a rule for querying or acting on it. In some cases the state is differentiable and trainable, as in the class-shared memory of few-shot semantic segmentation; in others it is explicit and symbolic, as in edit memories or event logs; and in systems work it may be low-level metadata or a device state encoded by physical vortices (Chen et al., 2024, Mitchell et al., 2022, Fu et al., 28 May 2026, Ziad et al., 25 Feb 2025, Kalashnikov et al., 2023).

Domain	Memory base form	Representative paper
Few-shot segmentation	Learnable class-shared memory vectors	(Chen et al., 2024)
Knowledge base completion	Per-entity superposition memories	(Lalisse et al., 2021)
Model editing	Explicit edit memory with retrieval and gating	(Mitchell et al., 2022)
Stateful LLM applications	Event and entity stores with operators	(Fu et al., 28 May 2026)
GPU memory safety	Allocation metadata: base, size, tag	(Ziad et al., 25 Feb 2025)
Main-memory emulation	Per-region latency, bandwidth, bit-error state	(Hirofuchi et al., 2023)
Superconducting memory	Integer number of Josephson vortices	(Kalashnikov et al., 2023)

This diversity shows that “memory base” is best understood as a systems-level abstraction rather than a single algorithm. In machine learning, the memory base typically regularizes generalization or preserves prior information. In infrastructure work, it defines the ground truth against which access validity, performance emulation, or device state is determined. A plausible implication is that the term is most useful when the stored state must persist across episodes, sessions, or physical operations, rather than being recomputed transiently.

2. Differentiable memory bases in representation learning

In few-shot semantic segmentation, the paper “Memory-guided Network with Uncertainty-based Feature Augmentation for Few-shot Semantic Segmentation” introduces a class-shared memory (CSM) consisting of $N=50$ learnable memory vectors, each in $\mathbb{R}^{256}$, trained end-to-end on base-class episodes and used during both training and inference for novel classes (Chen et al., 2024). For a query feature $f^q_j$, memory readout is a softmax-normalized dot-product attention over the memory bank,

$$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$

and the training objective is

$$L_{\mathrm{total}} = L_{\mathrm{seg}} + L_{\mathrm{recon}}.$$

The accompanying Uncertainty-based Feature Augmentation (UFA) perturbs per-channel statistics via Gaussian re-parameterization and mixes query and support statistics with $\lambda \sim \mathrm{Beta}(0.1,0.1)$. Quantitatively, MENUA improves BAM on PASCAL-5$^i$ from 67.81 to 69.24 in 1-shot and from 70.91 to 72.07 in 5-shot, and improves HDMNet from 69.40 to 70.22 in 1-shot and from 71.80 to 72.89 in 5-shot; on COCO-20$^i$, MENUA improves BAM from 46.23 to 47.74 in 1-shot and from 51.16 to 52.25 in 5-shot, and improves HDMNet from 50.00 to 50.94 in 1-shot and from 56.00 to 57.08 in 5-shot (Chen et al., 2024).

In few-shot class-incremental learning, “Few-shot Class-Incremental Learning via Generative Co-Memory Regularization” constructs a representation memory $M_e^{(t)}$ from class-mean features and a weight memory from classifier parameters and projected prototypes (Bao et al., 12 Jan 2026). Base training combines masked feature reconstruction and classification through

$$\mathcal{L}_{\mathrm{base}}=\alpha \mathcal{L}_{\mathrm{rec}} + (1-\alpha)\mathcal{L}_{\mathrm{cls}},$$

and incremental sessions optimize classification jointly with co-memory regularization. The representation memory stores 768d class means, projected features are 256d, and the memory footprint grows by about 3 MB for 1000 total classes. Reported results include 69.77 average accuracy on CIFAR100 and 70.26 on MiniImageNet with a ViT-B backbone (Bao et al., 12 Jan 2026).

In “GAN Memory with No Forgetting,” the memory base is a frozen pretrained GP-GAN plus per-task style parameters that modulate generator and discriminator weights through modified FiLM and AdaFM operations (Cong et al., 2020). Because the base weights and all previous task-specific styles are never changed, the method claims “no forgetting” under the stated assumptions. The six-task sequence includes Flowers, Cathedrals, Cats, Brain-tumor MRIs, Chest X-rays, and Anime faces at $\mathbb{R}^{256}$0, and style modulation uses about 20% of the trainable parameters versus full fine-tuning while achieving better FID and faster target-task training (Cong et al., 2020).

These works use memory bases to stabilize transfer under data scarcity. This suggests that, in representation learning, a memory base often acts as an anchor: class-agnostic patterns in CSM, class prototypes and classifier weights in GCMR, or reusable kernel “shape” information in GAN Memory.

3. Knowledge, model editing, and stateful interaction

In “Scalable knowledge base completion with superposition memories,” Harmonic Memory Networks construct a per-entity memory as a weighted superposition of relation–neighbor bindings, using either tensor product representations or circular convolution (Lalisse et al., 2021). Candidate neighbor–relation pairs are scored, the top-$\mathbb{R}^{256}$1 neighbors with $\mathbb{R}^{256}$2 are retained, and the memory is then completed by a learned quadratic Harmony function before unbinding with the query relation. The architecture supports on-the-fly representations for unseen entities and incremental graph evolution without retraining. On WN18, HMem-TPR+ reaches MRR .944, Hits@10 .960, and MR 174; on FB15K, HMem-TPRim reaches MRR .790, Hits@10 .886, and MR 24 (Lalisse et al., 2021).

In “Memory-Based Model Editing at Scale,” SERAC defines the memory base as a dynamic set $\mathbb{R}^{256}$3 of edit entries, each storing an edit descriptor and optionally a precomputed key for retrieval (Mitchell et al., 2022). At inference, the system retrieves the top-1 edit with a scope classifier and routes the input either to the unchanged base model or to a counterfactual model. The paper gives the soft formulation

$\mathbb{R}^{256}$4

while the implemented system uses a hard gate at 0.5. Memory per edit is reported as approximately 3 KB, and the method remains robust even with 75 simultaneous edits. On QA with T5-large, SERAC reaches Edit Success 0.986 and Drawdown 0.009; on QA-hard, 0.913 and 0.028; on FC, 0.877 and 0.051; and on ConvSent, 0.991 and 0.000 (Mitchell et al., 2022).

In “VikingMem: A Memory Base Management System for Stateful LLM-based Applications,” the Memory Base is formalized as an Event–Entity abstraction with selective extraction, stateful evolution, and generalizable operators such as SUM, COUNT, MAX, AVG, LLM_MERGE, and TIME_COMPRESS (Fu et al., 28 May 2026). Retrieval combines hybrid dense and sparse scoring with temporal and business weighting,

$\mathbb{R}^{256}$5

and temporal weighting uses a freshness window $\mathbb{R}^{256}$6 with exponential decay thereafter. Reported outcomes include up to about 30% improvement in memory retrieval effectiveness in the abstract, up to about 38% retrieval-accuracy improvement in the detailed results, one-pass extraction cost reduced by about $\mathbb{R}^{256}$7 versus multi-pass, storage reduced to about 16.82% of raw tokens on LongMemEval_s, and p50/p95 latency of about 0.20–0.25 s and 0.39–0.89 s (Fu et al., 28 May 2026).

These systems differ in purpose—completion, editing, and persistent interaction state—but all externalize information that would otherwise need to be encoded solely in model parameters or prompt context. This suggests that memory bases are especially attractive when locality, incremental updates, or long-horizon persistence are primary constraints.

4. Boundaries of memory use and safety

The presence of a memory base does not by itself determine when memory ought to be used. “When Should Memory Stay Silent: Measuring Memory-Use Boundaries in Memory-Augmented Conversational Agents” formulates the memory-use boundary problem as current-turn warrant: whether the present user turn provides sufficient justificatory basis for surfacing prior sensitive memory (Xu et al., 4 Jun 2026). RBI-Eval measures this with a condition-blind judge and an absolute separation score

$\mathbb{R}^{256}$8

where higher scores indicate more conservative memory use. Under memory access, the sensitive-history integration separation score decreases by 8.9%–26.6% for GPT-5.4-mini, but by 51.1%–82.9% for Claude-Sonnet-4.6, DeepSeek-V4-Flash, and Qwen3.5-9B. Retrieval reduces exposure, yet DeepSeek still shows conditional sensitive-history integration rates of 66.7%–94.9% once the sensitive target is exposed (Xu et al., 4 Jun 2026).

The results imply that retrieval-time filtering is necessary but not sufficient. The paper therefore recommends sensitivity detection and labeling, topic and warrant matching beyond semantic relevance, risk-aware ranking, exposure budgeting, generation-time ask-before-use behavior for high-sensitivity memories, and prompt-level boundary policies. In control settings, boundary-policy instructions raise DeepSeek Mem0 sensitive-integration BSS from 28.3 to 99.9 and keep GPT-5.4-mini near 100.0 (Xu et al., 4 Jun 2026).

This safety perspective complements the architectures above. SERAC models edit scope explicitly; VikingMem uses business and temporal weighting; RBI-Eval shows that even when retrieval is accurate, warranted use remains a separate decision problem. A plausible implication is that future memory-base systems will need distinct mechanisms for relevance, scope, and normative restraint.

5. Systems and hardware interpretations

In GPU memory safety, “GPUArmor: A Hardware-Software Co-design for Efficient and Scalable Memory Safety on GPUs” uses a memory base as per-allocation metadata: an 8-byte base address with temporal tag in the upper bits and an 8-byte size, stored in a disjoint device-side structure (Ziad et al., 25 Feb 2025). The compiler inserts LOADMETA and MEMCHECK, and a small per-SM Memory Lookaside Buffer with 8 entries caches metadata near the Load/Store Unit. Legal accesses satisfy the spatial predicate $\mathbb{R}^{256}$9 and the temporal predicate $f^q_j$0. GPUArmor reports about 2.3% average runtime overhead with binary tree plus 8-entry MLB, about 2.2% for GPUArmor-HWOnly, approximately 0.0005% metadata storage overhead, 100% detection for immediate use-after-free, and about 99.2% probabilistic detection for delayed use-after-free with $f^q_j$1 tags (Ziad et al., 25 Feb 2025).

In “METICULOUS: An FPGA-based Main Memory Emulator for System Software Studies,” the memory base is a hardware-controlled set of memory regions whose read latency, write latency, throughput, and bit-flip error rate are independently configurable at runtime (Hirofuchi et al., 2023). The rate controller is AXI4-compliant and sits between CPU-side masters and FPGA-side DRAM. Measured latency is exactly proportional to inserted latency, with minimum overhead of approximately 240 ns relative to CPU-side DRAM, and the FPGA-side base latency is approximately 400 ns. The platform supports independent bandwidth caps and error rates per region, enabling NUMA-like and NVDIMM-like experiments on unmodified software (Hirofuchi et al., 2023).

In “Josephson vortex-based memory,” the memory state is encoded by the integer number $f^q_j$2 of Josephson vortices in a long SNS Josephson junction embedded in a coplanar waveguide resonator (Kalashnikov et al., 2023). The device operates at 35 mK, uses low-power microwave excitation at $f^q_j$3 dBm and AC current of about 4 $f^q_j$4A, and distinguishes states through state-dependent resonance frequency and internal loss. For a 4.5 GHz resonator, the extracted values include $f^q_j$5 GHz and $f^q_j$6 for $f^q_j$7, versus $f^q_j$8 GHz and $f^q_j$9 for $$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$0. The numerical model estimates write energy of about 1 aJ, with practical local-control write times of about 40 ps and envisioned write times of about 6 ps for larger $$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$1 (Kalashnikov et al., 2023).

In content-centric networking, “Memory Efficient Forwarding Information Base for Content-Centric Networking” treats the forwarding information base itself as the memory substrate and studies hash-based and Bloom-filter-based designs for IoT nodes (Teubler et al., 2017). The hash design stores 32-bit prefix hashes with face bit-vectors, giving $$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$2 bits, while the Bloom-filter design uses one filter per face with standard sizing $$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$3. For large numbers of prefixes with equal distribution of prefixes to faces, the paper recommends Bloom filters; in all other cases, hashes are recommended (Teubler et al., 2017).

These systems papers use memory base in a more literal sense: authoritative metadata or physically encoded state that other components must trust. Here, update semantics, coherence, and bounded overhead are as important as representational capacity.

6. Limitations, trade-offs, and open directions

The surveyed works repeatedly expose capacity and interference trade-offs. In MENUA, memory size is sensitive: $$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$4 is best, while $$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$5, $$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$6, $$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$7, and $$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$8 underperform it; removing the reconstruction loss reduces performance from 69.24 to 67.81 on PASCAL-5$$a=\mathrm{Softmax}(f^q_j M^\top), \qquad \tilde f^q_j=aM,$$9 1-shot (Chen et al., 2024). In HMem, superposition interference grows with neighborhood size, and performance depends on top-$$L_{\mathrm{total}} = L_{\mathrm{seg}} + L_{\mathrm{recon}}.$$0 pruning, Harmony completion, and the choice of $$L_{\mathrm{total}} = L_{\mathrm{seg}} + L_{\mathrm{recon}}.$$1 (Lalisse et al., 2021). In GAN Memory, storage still grows linearly with the number of tasks unless compression is applied, and aggressive compression can worsen FID on later tasks (Cong et al., 2020).

A second recurring limit concerns update validity and retrieval precision. SERAC can fail under overlapping or conflicting edits because top-1 routing may pick the wrong edit, and retrieval errors remain a bottleneck on difficult fact-checking settings (Mitchell et al., 2022). VikingMem depends on LLM-based extraction, merging, and topic linking, which can introduce errors or biases, and its temporal compression policies are heuristic (Fu et al., 28 May 2026). RBI-Eval shows that even when memory is relevant, generation-time uptake can still be normatively inappropriate unless explicit boundary policies are present (Xu et al., 4 Jun 2026).

Infrastructure-oriented memory bases exhibit different failure surfaces. GPUArmor does not cover sub-object bounds and falls back to tagging-based detection for some inter-scope derivations (Ziad et al., 25 Feb 2025). METICULOUS does not model persistence instructions, failure-atomicity semantics, or detailed CXL protocol behavior, and it cannot emulate latencies below the platform’s approximately 400 ns FPGA-side base (Hirofuchi et al., 2023). Josephson vortex-based memory demonstrates reproducible switching and readout, but the paper does not report quantitative error rates, endurance, or retention times (Kalashnikov et al., 2023). Bloom-filter FIBs cannot delete without counting Bloom filters, and false positives can forward Interests to extra faces (Teubler et al., 2017).

Taken together, these results suggest that a memory base is rarely a universal remedy. It is a design choice that shifts difficulty from one locus to another: from parametric storage to retrieval and scope modeling, from raw history retention to compression and consistency, or from software checks to metadata coherence and physical encoding. The literature therefore points toward hybrid designs in which memory content, update operators, access control, and evaluation criteria are co-designed rather than treated as separable components.