Memix: DL-Driven Far-Memory System

• Memix is a Linux-based far-memory system that integrates deep-learning prefetching into the OS swap subsystem to minimize latency on remote memory accesses.
• It employs an offline training pipeline using a compact RetNet model and an in-kernel online predictor that resolves ordinal page misses with 1 μs latency.
• Experiments demonstrate that Memix outperforms traditional systems by up to 42% and issues up to 3x more useful prefetches under low local-memory ratios.

Memix is a Linux-based far-memory system for datacenters that uses a deep-learning-system co-design to prefetch pages from far memory to local DRAM, with the objective of minimizing on-demand far-memory accesses that bottleneck application performance. In the formulation reported in "An Early Exploration of Deep-Learning-Driven Prefetching for Far Memory," Memix is motivated by the observation that memory accesses are shaped by both application semantics and runtime context, and it therefore optimizes these two factors independently through offline learning and online mapping (Huang et al., 5 Oct 2025).

1. Definition and operating context

Far-memory systems place less-active data in more energy-efficient memory media, but they incur substantial latency when data must be fetched on demand from far memory back to local memory. Memix addresses this regime by integrating DL-driven prefetching into the far-memory path, rather than relying on simple rule-based predictors such as sequential or stride heuristics. The target setting is data-center infrastructure adopting network-attached or tiered non-local memory, including RDMA-attached DDR4 pools and related disaggregated memory configurations (Huang et al., 5 Oct 2025).

The system is presented as an OS-level mechanism rather than an application-level library. It is implemented as an in-kernel component integrated with the Linux swap subsystem, so its unit of operation is the 4KB memory page at swap granularity. This design situates Memix in the systems lineage of swap-based far-memory platforms such as FastSwap and Hermit, but with a different prefetching mechanism. A plausible implication is that the main novelty lies less in the existence of swapping to far memory than in the predictor architecture and its coupling to runtime address resolution.

2. Architectural decomposition

Memix has two main components: an offline training pipeline and an online prediction-and-prefetch component. The offline pipeline learns application memory-access semantics from representative traces using a compact neural model. The online component is deployed inside the kernel, monitors page faults, predicts future page misses, and issues asynchronous prefetches while the current fault is being serviced (Huang et al., 5 Oct 2025).

The architectural split is organized around semantic/context decoupling. Offline training captures repeatable access structure, whereas online execution maps model outputs to concrete runtime addresses through a dynamic “future map.” This separation is central because absolute addresses are not stable across runs and because direct address prediction would entail an impractically large vocabulary.

Component	Function	Location
Offline training pipeline	Learns application memory access semantics from representative traces	Offline
Online prediction & prefetch component	Predicts page misses and issues prefetches during page-fault handling	In kernel

A distinctive implementation choice is that all inference is performed on the same CPU core as the application, specifically to avoid context-switching and core oversubscription. The reported average inference latency is 1 microsecond, and the model size is 2.5K parameters, with the model fitting in L1/L2 cache. This places Memix in a regime where predictor invocation can be interleaved with page-fault processing without introducing a separate accelerator or service thread (Huang et al., 5 Oct 2025).

3. Prediction formulation and semantic/context decoupling

Memix does not predict absolute memory addresses. Instead, it predicts ordinals: the index from $0$ to $K-1$ of the next likely accessed page relative to the current page context, with default vocabulary size $K = 64$. The model input is a recent history of pairs consisting of page miss address modulo $K$ and program counter modulo $K$, written as

$$\{(\text{page address} \bmod K, \text{PC} \bmod K)\}^{h}.$$

The paper contrasts this with direct address prediction, whose address vocabulary size would be

$2^{36}$

for 4KB pages on 64-bit systems (Huang et al., 5 Oct 2025).

The DL model is RetNet, chosen because it is described as a transformer architecture with linear, that is, constant inference time, while still capturing non-linear and long-range dependencies in access sequences. The model is trained to learn semantic access patterns such as which data-structure element tends to follow a past sequence. The details state that the model learns these patterns in an input-agnostic fashion, which suggests an intended separation between structural access regularities and the specific virtual addresses materialized in a given execution.

At runtime, Memix resolves predicted ordinals into concrete addresses by maintaining a future map for each page $X$. That map records which concrete addresses have been observed to follow accesses to $X$, allowing the system to bind ordinal outputs to actual virtual addresses after observing a small amount of execution. This is the core of the claimed decoupling of application semantics from runtime context: semantics are modeled by DL, while instance-specific address realization is handled online (Huang et al., 5 Oct 2025).

4. Runtime execution path

The online path begins when the system observes a page fault, meaning a miss in local memory. During fault handling, Memix uses the trained model to predict future page misses and issues prefetches asynchronously in the background, overlapping prediction with far-memory RDMA I/O. The intention is to hide far-memory latency by converting future on-demand fetches into already-arrived local pages (Huang et al., 5 Oct 2025).

This runtime path depends on two constraints emphasized in the paper. First, predictor execution must be efficient enough for kernel deployment; the reported 1 microsecond latency and 2.5K-parameter RetNet satisfy that requirement. Second, prefetch utility depends on the sparse-graph nature of access behavior: most pages have a small number of likely next pages, which is why $K=64$ is presented as a practical setting. This suggests that Memix is designed for workloads with structured successor relations rather than purely random access.

The paper also identifies the principal failure mode of aggressive prefetching: swap-out pressure. Even if prefetches are accurate, bringing in more pages can increase evictions, potentially displacing useful local pages and degrading performance. Memix therefore improves only one side of the far-memory control loop—the fetch path—while leaving swap-out and eviction policy as an open optimization frontier (Huang et al., 5 Oct 2025).

5. Experimental platform and reported results

The experimental platform consists of a compute node with a 28-core Intel Xeon Gold 5512U and DDR5 DRAM, a memory node with a 16-core Intel Xeon Gold 5218 and DDR4 DRAM, and a 100Gbps RDMA interconnect. The setup is framed as representative of modern datacenters using network-attached far memory and also as a way to emulate reuse of retired servers for energy and carbon efficiency (Huang et al., 5 Oct 2025).

The evaluation compares Memix against two baselines: FastSwap, a Linux kernel swap-based far-memory implementation using simple sequential prefetching, and Hermit, which improves swap-out handling but retains the same prefetching policy as FastSwap. The benchmarks are XGBoost, GAP-PageRank, and SPEC 2006 MCF, chosen to represent machine learning, graph processing, and data-intensive workloads with non-sequential access behavior.

Several quantitative claims are reported. Preliminary evaluation shows that Memix outperforms the state-of-the-art far-memory system by up to 42%. At low local-memory ratios such as 30% of working set, Memix issues up to 3x more useful prefetches. The experimental methodology measures normalized execution time as a function of local-memory fraction, with all experiments normalized to full-local DRAM runs. The details state that Memix consistently provides lower end-to-end run times and is more robust to local-memory shortage owing to superior prefetching (Huang et al., 5 Oct 2025).

6. Scope, implications, and limitations

Memix is positioned for data centers adopting memory tiering, disaggregation, and related far-memory deployments. The details explicitly connect its relevance to RDMA-attached far memory and to future settings involving CXL and heterogeneous memory. Because it is swap-integrated and OS-level, it does not require application source changes. A plausible implication is that this lowers deployment friction relative to application-specific prefetch mechanisms, although the paper does not quantify operational cost beyond the reported kernel integration.

The paper associates Memix with broader efficiency goals. By reducing remote memory stalls, it enables CPUs to idle more frequently and thereby complements the energy-saving rationale of far memory. The details also state that reusing old DRAM or servers as far memory can contribute up to 20% data-center carbon savings, though that figure pertains to the broader infrastructure motivation rather than to a measured end-to-end Memix result (Huang et al., 5 Oct 2025).

The stated limitations are equally specific. Memix is best suited to applications with repeated memory-access paths, including tree traversals and iterative analytics. Efficacy is lower for pure-random or hash-based workloads, where access is not well correlated with recent history. Training is offline and per application, or per significant input drift, with a reported training time of about 30 minutes on a single NVIDIA A6000 GPU. Open directions include joint optimization of prefetch, swap-out, and eviction policies; support for heterogeneous CXL-attached memory; handling multi-tenancy and co-located workload interference; and generalizing semantic/context decoupling to more irregular workloads. These caveats delimit Memix as an early exploration rather than a fully generalized far-memory control plane (Huang et al., 5 Oct 2025).