Max-Affine Lower-Bound Runtime Model

• The paper introduces a max-affine runtime model that accurately predicts per-timestep performance on Loihi 2 by integrating compute and communication cost metrics.
• Key methodology involves microbenchmarking five system constants and applying a roofline analysis to pinpoint compute versus communication bottlenecks.
• Empirical validation shows high predictive fidelity (r ≥ 0.97), enabling targeted hardware optimizations and efficient kernel design.

The max-affine lower-bound runtime model is a quantitative performance model originally introduced for Intel’s Loihi 2 neuromorphic chip, designed to provide a rigorous, simple, and predictive lower bound for per-timestep runtimes of neuromorphic workloads. By accounting for both compute and communication costs—including complex Network-on-Chip (NoC) congestion patterns—the model delivers a multi-dimensional “roofline” abstraction for predicting and analyzing tight lower bounds on application performance, underpinning both kernel design and architecture-aware optimization strategies (Timcheck et al., 15 Jan 2026).

1. Formal Definition of the Max-Affine Lower-Bound Model

At its core, the max-affine lower-bound runtime model combines four fundamental affine cost terms, corresponding to the principal computational and communication bottlenecks encountered in neuromorphic hardware operation. For each timestep of an algorithm on Loihi 2, the following operations are considered:

• Dendrite (neuron update) operations (DendOps)
• Synaptic multiply–accumulate operations (SynOps)
• Synaptic memory reads (SynMem-reads)
• Inter-core spike-message bits traversing the NoC

After each timestep, a barrier synchronization is performed. Because compute and communication only partially overlap, the strict lower bound on per-timestep runtime $T$ is given by:

$$T = \max \Bigl( N_{\rm DO} T_{\rm DO},\; N_{\rm SO} T_{\rm SO},\; N_{\rm SMR} T_{\rm SMR},\; \frac{N_{\rm LL}}{B},\; T_{\rm BS} \Bigr)$$

where:

• $N_{\rm DO}$: Maximum number of DendOps per NeuroCore in one timestep
• $T_{\rm DO}$: Effective time per DendOp (from microbenchmark)
• $N_{\rm SO}$: Maximum SynOps per NeuroCore per timestep
• $T_{\rm SO}$: Effective time per SynOp (from microbenchmark)
• $N_{\rm SMR}$: Maximum SynMem-reads per NeuroCore per timestep
• $T_{\rm SMR}$: Effective time per SynMem-read (from microbenchmark)
• $N_{\rm LL}$: Number of bits injected into the most-congested NoC link per timestep (measured via TrafficStats)
• $B$: Link bandwidth (bits per second, microbenchmarked)
• $T_{\rm BS}$: Barrier-synchronization time per timestep (microbenchmarked)

This max-affine formulation ensures each physical or architectural bottleneck is accounted for, and the effective runtime can be interpreted as being limited by the most expensive (in time) of these contributions (Timcheck et al., 15 Jan 2026).

2. Model Calibration and Roofline Visualization

To instantiate the model for a target Loihi 2 device, five system constants are microbenchmarked:

• $T_{\rm DO}$ (DendOp time)
• $T_{\rm SO}$ (SynOp time)
• $T_{\rm SMR}$ (SynMem-read time)
• $B$ (link bandwidth)
• $T_{\rm BS}$ (barrier-synchronization time)

Application-specific parameters $N_{\rm DO}$, $N_{\rm SO}$, $N_{\rm SMR}$, and $N_{\rm LL}$ are then measured or statically determined per workload, with $N_{\rm LL}$ most conveniently retrieved from NoC traffic statistics. The model thus yields a multi-dimensional roofline analysis, analogous to classical roofline models for computational science. When plotted as time versus “arithmetic intensity” (operations/communication), the transition between compute-bound and communication-bound behavior is made explicit, thus revealing which subsystem is performance-limiting for a given workload configuration (Timcheck et al., 15 Jan 2026).

3. Compute- vs. Communication-Boundedness and Piecewise Runtime Forms

The max-affine form directly delineates compute-bounded and communication-bounded regimes. Considering only the two most prominent terms (for clear illustration):

$$T = \begin{cases} N_{\rm SO}\,T_{\rm SO}, & \text{if } N_{\rm SO}\,T_{\rm SO} \ge N_{\rm LL}/B \ N_{\rm LL}/B, & \text{otherwise} \end{cases}$$

In practice, the maximum is always taken over all four affine terms. The explicit formulation allows determination, for each kernel, of whether compute (e.g., SynOps) or communication (NoC traffic) is dominant, guiding subsequent optimization efforts (Timcheck et al., 15 Jan 2026).

A closely related parametric roofline approach for general affine programs—distinct from the detailed hardware microbenchmarking of Loihi 2—is documented in (Olivry et al., 2019), where lower bounds on runtime are similarly captured as $T \ge \max\{ W/P,\, Q/B \}$ with $W$ representing total work (flops), $P$ peak flops/s, $Q$ data movement lower bound, and $B$ bandwidth.

4. Analytical Treatment of Network-on-Chip Congestion and Area–Runtime Trade-Offs

Communication bottlenecks in large-scale workloads are analytically characterized using router occupancy matrices $P_{ij}$ describing core placements within the NoC. For a fully connected linear layer of $M$ origin and $M$ destination NeuroCores (each with $N$ neurons), the maximal left-ward router-to-router link load is:

$$N_{\rm LL}^{\rm (r \to r)} = \max_{i,l} \left[ \Bigl(\sum_{j=l}^{m} P_{ij}\Bigr) \Bigl(\sum_{l'=1}^{l-1} \sum_{k=1}^n P_{kl'}\Bigr) \right]$$

Notably, for various placements:

• Saturated square ($P_{ij} = 1,\, n=m,\, M=n^2$):

$N_{\rm LL} \approx n^3/4 = M^{3/2}/4$ (superlinear in $M$)

• X-shaped placement (populated diagonals of $n \times n$ grid, $M=2n$):

$N_{\rm LL} = 2(n-1) = M-2$ (linear in $M$)

The area required by NoC routing grows as the number of routers ($\sim M$ for square, $\sim M^2/4$ for X-shape), leading to an explicit area–runtime trade-off. Compact (square) tilings minimize area but induce superlinear congestion, while spread (X-shaped) placements lower the bottlenecked runtime at the expense of increased on-chip area (Timcheck et al., 15 Jan 2026).

5. Empirical Validation and Predictive Power

The model’s tightness and practical effectiveness have been extensively validated:

• Dense linear layer (matrix–vector multiply): Up to 120 NeuroCores, 256 neurons/core, 1–8 bit weights; measured versus predicted time shows Pearson $r = 0.996$.
• Tiled-identity linear layer under variable placements (traffic-bottlenecked): $r = 0.999$.
• QUBO solver (recurrent, alternating "checking" and "switching" stages): Mean time per step, predicted versus measured, $r = 0.970$.

Across these workloads, the model remains a strict lower bound with $r \ge 0.97$ correlation between predicted and observed runtimes, demonstrating high predictive fidelity even as a lower-bound approach (Timcheck et al., 15 Jan 2026).

6. Practical Application, Strengths, and Limitations

A brief practical application workflow involves:

1. Microbenchmarking Loihi 2: Measure $$\{T_{\rm DO}, T_{\rm SO}, T_{\rm SMR}, B, T_{\rm BS}\}$$.
2. Workload Parameterization: Count $N_{\rm DO}, N_{\rm SO}, N_{\rm SMR}$ per NeuroCore, obtain $N_{\rm LL}$ via TrafficStats.
3. Runtime Estimation: Compute $T$ using the max-affine equation.
4. Bottleneck Diagnosis: The dominating term indicates whether the bottleneck is SynOps, memory reads, or NoC traffic—informing retile or redistribution strategies.

Key strengths include conceptual simplicity, requirement for only five system constants and per-kernel integer counts, explicit bottleneck identification, tight empirical lower bounding (correlation $r\gtrsim 0.97$), and immediate core placement guidance.

Limitations: The current model is restricted to “fall-through” single-kernel runtimes, excludes multi-kernel pipelined congestion, lacks modeling of special-purpose stages and barrier-release overheads, and presently has no energy model, though energy extensions are planned (Timcheck et al., 15 Jan 2026).

7. Broader Context and Connection to Affine Program Roofline Models

The max-affine lower-bound model is conceptually aligned with established roofline models used in classical high-performance computing to characterize lower bounds on runtime as the maximum of compute- and communication-driven constraints. This tradition is illustrated in (Olivry et al., 2019), where the runtime lower bound for generic affine programs

$$T \geq \max \biggl\{ \frac{W}{P},\, \frac{Q}{B} \biggr\}$$

is systematically derived for matrix–matrix multiply (GEMM), matrix–vector multiply (GEMV), and 2D convolution (CONV2D). In these cases, $W$ is the arithmetic workload, $Q$ is the minimal data movement, $P$ is computational throughput, and $B$ is communication bandwidth—mirroring the structure and guiding philosophy of the Loihi 2 max-affine model.

A plausible implication is that the max-affine approach offers a general template for performance modeling in architectures where overlapping compute and communication is partial, bottlenecks are quantifiable via microbenchmarks or static parameters, and architectural congestion or area-trade-offs are material (Timcheck et al., 15 Jan 2026, Olivry et al., 2019).