LoReB Hybrid Pipeline for FFT Computation

• The paper presents a unified architecture integrating pipelined and memory-based methods to reduce FFT stage count by up to 40%.
• LoReB Hybrid Pipeline is defined by its modular reconfigurability using high-radix MDC units and advanced permutation schemes for conflict-free memory access.
• Empirical benchmarks on FPGA show superior throughput and area efficiency, with hardware utilization rates of 60-80% for varying degrees of parallelism.

The LoReB Hybrid Pipeline denotes an architecture class integrating pipelined and memory-based strategies for fast Fourier transform (FFT) computation, particularly utilising high-radix multi-path delay commutator (MDC) modules and sophisticated permutation schemes to ensure adaptability, high utilization, and conflict-free memory access on large-scale hardware. It is characterized by modular reconfigurability between continuous-flow (pipelined) and in-place (memory-based) operation for various signal sizes and degrees of parallelism, as detailed in "Adaptive Hybrid FFT: A Novel Pipeline and Memory-Based Architecture for Radix-$2^k$ FFT in Large Size Processing" (Zhao et al., 2 Jan 2025).

1. Architectural Overview

The pipeline combines front-end pipelined MDC units (enabling high throughput) with a back-end in-place memory-processing subsystem (optimized for area efficiency during large-size signal handling). Its block-level structure includes:

• Data-Reordering Module: 2P single-port memory banks for real/imaginary samples, with address-generation and bit-dimension permutation units (denoted as σ₁, σ₂, σ₃).
• FFT Core Processor: P parallel MDC units, each instantiated for radix-$2^k$ butterfly structures.

Operational modes:

• Pipeline Mode ($N \leq 2^{4k}$): Each stage’s MDCs operate across two independent bank sets; output flows horizontally, stage by stage, maximizing data throughput.
• Memory-Based Mode ($N \leq 2^{3k}$): A single set of banks is reused; data is reordered and streamed in-place for multiple iterations, focusing on hardware area conservation.

2. Radix-$2^k$ MDC Unit Design

The pipeline implements generalized DFT computation: $$X(k) = \sum_{n=0}^{N-1} x(n) W_N^{nk}, \quad W_N = e^{-j2\pi/N}$$ with multi-dimensional index mappings for radix-$2^k$ factorization. Stage $s$ applies radix-$2^{k_s}$, where $N=2^n$, $2^k$0, and $2^k$1 stages. Twiddle factors are decomposed into constant ($2^k$2), trivial ($2^k$3), and non-trivial ($2^k$4) rotators, positioned between delay lines and butterfly chains.

Each MDC block comprises:

• A chain of radix-2 butterflies for $2^k$5 inputs.
• Rotator circuits realizing $2^k$6, $2^k$7, and $2^k$8 twiddle factor multiplications.
• Multiplexers for selectively bypassing hardware under lower-radix operation.

Reference graph instantiation for radix-$2^k$9 (32-point) comprises five stages coded as C→T→C→T→NT.

3. Conflict-Free Memory Access

To preserve continuous dataflow and atomic read/write transactions:

• Pipeline Mode: Circular counters generate raw addresses partitioned into bank and offset fields. Bit permutations (σ₁ for reads, σ_R^i/σ_W^i for write/read interleaving) alternate natural and reversed bit patterns, strictly avoiding cross-bank collisions.
• Memory-Based Mode: Dual complementary permutations (σ_{N,1} and inverse-prefix $N \leq 2^{4k}$0) are composed to compute memory access paths ($N \leq 2^{4k}$1) ensuring address space disjointness at each iteration.

In both modes, bank mapping resolves the $N \leq 2^{4k}$2 MSBs of permuted addresses, with LSBs used for intra-bank offsetting.

4. Bit-Dimension Permutation Strategy

End-to-end permutation from stage $N \leq 2^{4k}$3 output to stage $N \leq 2^{4k}$4 input is formalized as: $N \leq 2^{4k}$5

• σ₁ (Serial-Bit Reversal): Inverts $N \leq 2^{4k}$6 LSBs, where $N \leq 2^{4k}$7 is context-sensitive to radix, bank count, and stage index.
• σ₂ (Parallel-Branch Reversal): Reverses $N \leq 2^{4k}$8 MSBs across parallel banks.
• σ₃ (Reshuffle): Swaps bits between offsets and branches as required by MDC interconnect, potentially cascading up to six stages for large $N \leq 2^{4k}$9 and depth.

5. Data Flow and Reordering Algorithm

Stage-wise data handling is encapsulated in the following pseudo-code (direct from (Zhao et al., 2 Jan 2025)): $$X(k) = \sum_{n=0}^{N-1} x(n) W_N^{nk}, \quad W_N = e^{-j2\pi/N}$$3 In pipeline mode, alternate bank sets receive output; in memory-based mode the same array is re-read and overwritten iteratively.

6. Benchmark Results and Performance Analysis

The LoReB design yields improved iteration counts, computation times, and hardware utilization versus prior art:

Design	Iterations	Cycle Time (for $N \leq 2^{3k}$0)
Tsai’11 (radix-2…2³)	$N \leq 2^{3k}$1	$N \leq 2^{3k}$2
Kaya’23 (radix-2)	$N \leq 2^{3k}$3	$N \leq 2^{3k}$4
Wang’20 (radix-2…2³)	$N \leq 2^{3k}$5	$N \leq 2^{3k}$6
LoReB (radix-2…2⁵)	$N \leq 2^{3k}$7	$N \leq 2^{3k}$8

FPGA implementation (Xilinx VCU118, xcvu9p) delivers:

• DSP48E2 slices: $N \leq 2^{3k}$9
• LUTs: $2^k$0
• Flip-Flops: $2^k$1
• BlockRAM: $2^k$2 × 36 Kb
• UltraRAM: $2^k$3 × 288 Kb
• Maximum Clock: $2^k$4 MHz
• Throughput for $2^k$5, $2^k$6: approximately $2^k$7

Hardware utilization data indicate LoReB maintains $2^k$8 utilization for $2^k$9, and $$X(k) = \sum_{n=0}^{N-1} x(n) W_N^{nk}, \quad W_N = e^{-j2\pi/N}$$0 for deeper parallelism (see comparison with Garrido’13 [radix-2⁵]).

7. Contextual Significance and Implications

LoReB’s key contributions are:

• Unified architecture for both pipelined and memory-based FFT operations.
• Radix-$$X(k) = \sum_{n=0}^{N-1} x(n) W_N^{nk}, \quad W_N = e^{-j2\pi/N}$$1 MDC implementation enabling up to $$X(k) = \sum_{n=0}^{N-1} x(n) W_N^{nk}, \quad W_N = e^{-j2\pi/N}$$2 reduction in stage count versus radix-2/2³ designs.
• General permutation strategies compatible with arbitrary signal length, radix, and parallelism.
• Demonstrated superior hardware resource efficiency and throughput for large-scale applications.

The conflict-free permutation logic and MDC-based computation position LoReB as a scalable solution for configurable, high-performance FFT processors in contemporary digital signal processing pipelines (Zhao et al., 2 Jan 2025). A plausible implication is applicability in domains requiring reconfigurable throughput-to-area trade-offs without manual redesign. The formalization of data-dependent address permutations also suggests potential cross-applications in more general high-radix signal transformation circuits where data contention is a bottleneck.