Long-term RAM (LtRAM) Technology

• Long-term RAM (LtRAM) is a memory technology that bridges DRAM and persistent storage by combining DRAM-like read latency with higher density and energy-efficient performance.
• LtRAM targets read-intensive, long-lived workloads, benefitting applications such as LLM inference, in-memory datastores, and static code libraries with reduced energy and cost.
• System integration of LtRAM requires OS-level management with specialized page migration and Application Read-Only Memory (AROM) protocols to overcome write latency and endurance constraints.

Long-term RAM (LtRAM) is a distinct class of main-memory technology designed to bridge the gap between conventional DRAM and persistent storage. It targets workloads characterized by read-dominated access patterns and data with lifetimes extending from minutes to years. LtRAM achieves DRAM-comparable read latency with significantly higher density and lower energy for reads, but accepts moderate write latency and endurance constraints as a trade-off for lower cost per bit and improved scalability. System integration relies on explicit operating system (OS) support for non-hierarchical memory classes and new page management protocols, such as Application Read-Only Memory (AROM), to mitigate device-level drawbacks and maximize system-wide efficiency (Li et al., 5 Aug 2025, Shim et al., 18 Jun 2026).

1. Characterization and Device Properties

LtRAM is optimized for read-intensive, long-lived data. The principal device attributes, with ranges as reported in (Li et al., 5 Aug 2025) and (Shim et al., 18 Jun 2026), are:

• Read Latency: Typically 15–300 ns. DRAM-competitive for several candidate technologies (e.g., MRAM, V-ReRAM, FeFET).
• Write Latency: 50 ns to 10 µs. Generally several-fold to orders-of-magnitude slower than reads.
• Read Energy: 1–5 pJ/bit (2–5× lower than DRAM).
• Write Energy: 5–15 pJ/bit (1–3× DRAM).
• Data Retention: Tens of minutes up to years. Nonvolatile or semi-nonvolatile per media type; no periodic refresh required.
• Endurance: $10^5$ to $10^{12}$ write cycles per cell (media-dependent).
• Cost per Byte: $2–8/GB$ is projected, between DRAM ($8–12/GB$) and NAND Flash ($0.1–0.5/GB$). High-density stacks (e.g., 3D V-ReRAM) enable projections of 2–10× DRAM capacity per package.

Representative parameters for major media types are summarized below.

Technology	Read Latency	Write Latency	Endurance (cycles)	Density vs. DRAM	Cost per Bit
DRAM	10–120 ns	10–120 ns	∞	1×	high
PCM	50–300 ns	100 ns–1 µs	$10^8$–$10^9$	1–2×	mid
MRAM	10–20 ns	15–30 ns	$>10^{12}$	0.5×	high
3D V-ReRAM	30–100 ns	80 ns–1 µs	$10^6$–$10^9$	2–10×	low
3D FeFET	~200 ns	~10 µs	$10^{12}$0	2–10×	low

This physical property space positions LtRAM as a dense, energy-efficient substrate for system memory, especially effective when writes are rare and reads dominate.

2. Distinction from Conventional RAM Classes

LtRAM is situated between SRAM, DRAM, StRAM (short-term RAM), and NAND/flash, differing in several critical aspects:

• SRAM: Ultra-low latency (~1 ns) but extreme cost per bit and static power, fitting only on-chip caches. LtRAM trades some latency for 10–100× higher density and much lower leakage but is unsuitable for on-chip scratchpads.
• DRAM: Moderate latency (10–120 ns), volatile, requires frequent refresh, and features destructive reads. LtRAM removes the refresh overhead (improving energy and retention), is nonvolatile, but can only tolerate moderate write rates due to finite endurance.
• StRAM: Designed for ephemeral data (activation buffers, queues), with symmetric R/W performance, high endurance, but sub-second retention. LtRAM targets persistent, read-mostly data, supporting much longer lifetimes and higher density at the cost of asymmetric performance and endurance.
• NAND/Flash: Much higher density and lowest cost per bit, but orders-of-magnitude lower bandwidth and much higher latency.

A system memory stack exposing SRAM, StRAM, DRAM, LtRAM, and NAND as explicit VM classes allows the OS to optimally place data based on observed access patterns (Li et al., 5 Aug 2025).

3. LtRAM System Integration and OS Management

LtRAM integration requires significant redesign in both hardware and system software due to unique device-level constraints: read/write asymmetry, coarse write granularity, and limited endurance.

OS Classification and Page Migration:

• OS tracks per-page read and write counts over epochs. Pages satisfying $10^{12}$1 and $10^{12}$2 are migrated to LtRAM (read-mostly, cold pages); frequent writers remain in StRAM/DRAM (Li et al., 5 Aug 2025).
• Pseudocode for classification/migration:

$2–8/GB$5

Application Read-Only Memory (AROM):

• LtRAM is made read-only at the application level; only the OS may write (typically for page migration or initialization). Application write attempts trigger copy-on-write (CoW): a page is faulted to DRAM, allowing the store to proceed and thus eliminating the need for hardware translation layers or on-DIMM wear-leveling (Shim et al., 18 Jun 2026).
• OS manages wear-leveling through a token-based approach: for $10^{12}$3 pages, endurance $10^{12}$4, intended lifetime $10^{12}$5, migration rate is $10^{12}$6.
• Physical address maps and TLBs are extended to expose memory class-specific channels and optimize routing at the hardware level.

Controller and Bus Protocol:

• LtRAM modules are mapped separately (e.g., 0x1000_0000–0x1FFF_FFFF) and can be attached via DDR-style or dedicated NVM bus. Controllers can be made simpler by enforcing OS-only page-aligned writes, bypassing the need for fine-grained on-DIMM translation layers (Shim et al., 18 Jun 2026).

4. Device and Cost Modeling

The projected cost per bit advantages arise from both die cost and scalability:

$10^{12}$7

where $10^{12}$8 is die cost/area and $10^{12}$9 is raw density.

Energy per bit modeled as:

$2–8/GB$0

where $2–8/GB$1 is the write/read ratio for a workload.

Scaling trends (e.g., V-ReRAM projecting up to $2–8/GB$2 HBM density at advanced nodes) suggest that LtRAM density and cost efficiency may significantly outpace DRAM as process nodes shrink further (Li et al., 5 Aug 2025).

A plausible implication is that, if process maturity is maintained, LtRAM’s cost-per-bit can approach that of NAND Flash for specific high-density applications.

5. Example Workloads and Quantitative Evaluation

LtRAM’s utility is maximized in read-dominated, long-retention workloads where write frequency is both low and predictable:

• LLM Inference: Model weights are read-only during inference. Migrating weights to LtRAM yields a 30% reduction in memory energy (due to no DRAM refresh), a 20% lower cost per GB (with 3D V-ReRAM), and throughput within 5% of pure DRAM (Li et al., 5 Aug 2025). In MRM prototype, I/O energy per inference is reduced by 40%, and the endurance requirement (one update per 30 days) falls well within media limits.
• In-Memory Datastores: Read-heavy key–value workloads (Redis, Elasticsearch) storing hot indices in LtRAM result in a 2× reduction in average query latency and 25% lower system-level power versus DRAM.
• Code and Shared Libraries: Static code pages, when resident in LtRAM, lower system DRAM usage by 15% and reduce server OPEX by approximately $1,000 annually per machine.
• System Overheads: LtRAM with AROM interface recovers 26–79% of read latency inflation versus traditional translation-layered controllers (e.g., Optane), and can match or beat DRAM latency if fast nonvolatile media are employed (e.g., STT-MRAM) (Shim et al., 18 Jun 2026).

6. Drawbacks and Mitigations

Critical drawbacks are:

• Asymmetric R/W Latency: Writes are up to 50× slower than reads. Mitigation: Eliminate fine-grained app writes via AROM; batch page-aligned writes in the OS (Shim et al., 18 Jun 2026).
• Limited Endurance: Typically $2–8/GB$3–$2–8/GB$4 for most candidate media. Mitigation: Token-based wear leveling at the OS, limiting page writes and deferring migrations as needed.
• Coarse Write Granularity: Many media require 256 B–4 KB writes/erases, complicating random fine-grained access. Mitigation: Force OS to write full pages only, eliminating need for read-modify-write and hardware-level address translation.
• System Integration Complexity: System software must manage data placement, wear-leveling, and migration, necessitating new policies but yielding a dramatic hardware simplification and operational efficiency.

7. Research Outlook and Significance

LtRAM fills a fundamental gap in modern memory hierarchies, enabling scalable deployment of dense, energy-efficient, and DRAM-comparable memory for emerging read-most, long-lived workloads. Its adoption demands hardware-software co-design, including explicit abstraction of memory classes in OSes, page migration strategies matching workload temporal locality, and new management policies for endurance and page placement. By shifting complexity into the OS through the AROM model, LtRAM can avoid traditional NVM controller inefficiencies and unlock main-memory scaling at reduced cost (Li et al., 5 Aug 2025, Shim et al., 18 Jun 2026).

This architectural direction is poised to reshape server and datacenter system design, particularly as memory cost, energy, and scaling constraints increasingly dictate the performance and economics of large-scale computation.