Lexicographic One’s Complement Unpacking

• Lexicographic One’s Complement Unpacking is a technique that transforms floating-point codewords with a single XOR-mask to achieve lexicographic order for efficient integer comparisons.
• It addresses area, power, and latency bottlenecks in AI datapaths by eliminating hidden-bit normalization and multi-stage comparison logic.
• The method extracts sign, exponent, and mantissa via simple bias subtraction and wire slicing, leading to significant reductions in MAC unit area, power consumption, and critical-path delay.

Lexicographic One’s-Complement Unpacking is a combinational technique for floating-point codeword interpretation that ensures monotonic sorted order under integer comparison and enables ultra-low-latency field extraction of sign, exponent, and mantissa. Conceived as a solution to area, power, and latency bottlenecks in massively parallel AI datapaths, it underpins the “AetherFloat” family of block-scale-free quad-radix floating-point formats. Lexicographic One’s-Complement Unpacking is characterized by the application of a single XOR-mask transformation that cancels the architectural need for hidden bits, normalization microcode, or multi-stage comparison trees, and decouples dynamic scaling from inference hardware (Morisaki, 26 Feb 2026).

1. Motivation in AI Datapaths

Conventional IEEE 754 and sign-magnitude floating-point encodings struggle in ultra-parallel neural processing units (NPUs) due to several structural limitations: non-monotonicity under two’s-complement integer comparison, the hidden-bit normalization requirement, and subnormal number handling overhead. In practical terms, this undermines key datapath operations:

• Multi-stage comparison is required for elementwise ReLU, MaxPooling, and similar ops, since two’s-complement ordering of bitfields does not correspond to actual floating-point value order.
• Hardware must trap and handle subnormals via microcoded logic, further inflating critical-path complexity and area.
• A normalization step is necessary to reconstitute the “hidden” leading 1 for normal numbers, requiring additional gates and pipeline stages.

Lexicographic One’s-Complement Unpacking directly addresses these issues by mapping raw codewords to a representation that is lexicographically aligned with true floating-point order and straightforward to unpack, requiring only a single XOR-mask operation and bias subtraction (Morisaki, 26 Feb 2026).

2. Mathematical Definition and Bit-Level Mapping

Given an $N$-bit codeword $x_{N-1} \ldots x_0$ with sign bit $S = x_{N-1}$, the unpacking sequence proceeds as follows:

1. Sign-Replicated Mask: $\mathbf{m}_i = S$ for $i = 0,\ldots,N-1$ (a bitvector of $S$).
2. Payload Transformation: $U = (x \oplus m) \wedge (2^{N-1}-1)$, which applies one’s-complement (XOR with $S$) to each bit except $S$ itself.
3. Field Extraction:
   • Exponent: $E' = u_{N-2} \ldots u_{M_\text{bits}}$
   • Mantissa: $x_{N-1} \ldots x_0$0
4. Exponent Decode:

$x_{N-1} \ldots x_0$1

$x_{N-1} \ldots x_0$2

1. Mantissa Fraction:

$x_{N-1} \ldots x_0$3 (No normalization step. Underflow: if $x_{N-1} \ldots x_0$4, leading bits may be zero)

2. Reconstitution of Real Value:

$x_{N-1} \ldots x_0$5

This mapping ensures that a signed integer comparison of two codewords is equivalent to a floating-point value comparison, thus enabling zero-cycle max/min and related logic (Morisaki, 26 Feb 2026).

3. Hardware Realization and Gate-Level Logic

The hardware implementation is purely combinational:

• Input: $x_{N-1} \ldots x_0$6-bit codeword $x_{N-1} \ldots x_0$7.
• Stage 1: Generate sign mask $x_{N-1} \ldots x_0$8 (bit-replication of $x_{N-1} \ldots x_0$9).
• Stage 2: Apply XOR to $S = x_{N-1}$0 and $S = x_{N-1}$1, mask payload.
• Stage 3: Extract exponent and mantissa slices as wire subfields.
• Stage 4: Exponent decode uses a compact zero-detect and +1 increment when $S = x_{N-1}$2 is zero.
• Stage 5: Subtract bias (single adder) to obtain final exponent.

There are no barrel shifters, hidden-bit normalization paths, or multi-cycle logic. Pipeline stages in a typical multiply-accumulate (MAC) datapath would include:

Stage	Operation(s)	Result
Stage 1	XOR-mask, field extraction	$S = x_{N-1}$3, $S = x_{N-1}$4, $S = x_{N-1}$5
Stage 2	Zero-detect($S = x_{N-1}$6), conditional increment, bias subtraction	$S = x_{N-1}$7
Stage 3	Mantissa scaling, alignment or multiplier input	$S = x_{N-1}$8, ready for subsequent computation

This direct mapping supports constant-time unpacking and enables the use of native integer comparators for floating-point operations (Morisaki, 26 Feb 2026).

4. Explicit Example: AF8 Unpacking Walkthrough

Given AF8 parameters ($S = x_{N-1}$9, $\mathbf{m}_i = S$0, $\mathbf{m}_i = S$1, $\mathbf{m}_i = S$2), consider $\mathbf{m}_i = S$3:

1. $\mathbf{m}_i = S$4
2. Mask: $\mathbf{m}_i = S$5 (all ones)
3. $\mathbf{m}_i = S$6 mask: $\mathbf{m}_i = S$7
4. $\mathbf{m}_i = S$8 splits: $\mathbf{m}_i = S$9, $i = 0,\ldots,N-1$0
5. Since $i = 0,\ldots,N-1$1, $i = 0,\ldots,N-1$2. $i = 0,\ldots,N-1$3.
6. Mantissa $i = 0,\ldots,N-1$4
7. Real value $i = 0,\ldots,N-1$5

Applying a signed integer comparison to the raw bit pattern yields a sorting order that matches the true floating-point interpretation, thus eliminating the need for floating-point comparator logic (Morisaki, 26 Feb 2026).

5. Archetypal HDL/Pseudocode Templates

Zero-latency unpacking can be succinctly realized in either C++-style or Verilog-style HDL. For example, in C++-like form:

$S$1

The minimalistic logic extends analogously in Verilog for direct hardware synthesis. The key primitive is the application of the XOR-mask, followed by direct wire slicing and a small subtractor (Morisaki, 26 Feb 2026).

6. Comparative Analysis: Costs, Benefits, and Trade-Offs

Lexicographic One’s-Complement Unpacking yields multiple hardware benefits:

• Area: Minimal gate count (one XOR row, one small subtractor). AF8 multiplers plus unpacking logic show a $i = 0,\ldots,N-1$6 reduction in MAC unit area versus a classical 8-bit FP+hidden-bit approach.
• Power: Fewer switching carry elements; elimination of barrel shifter traps. $i = 0,\ldots,N-1$7 total MAC power reduction (with $i = 0,\ldots,N-1$8 dynamic toggle reduction).
• Latency: Integer comparability (e.g., ReLU implemented as a signed int compare); no pipeline stalls on subnormals. $i = 0,\ldots,N-1$9 critical-path delay reduction.

The primary trade-off is the absence of the “hidden” leading mantissa bit: effective signal-to-quantization-noise ratio (SQNR) is $S$0 lower than a comparable base-2 format at fixed bit width. QAT (quantization-aware training) is required at lower bitwidths (e.g., AF8), rather than straightforward PTQ (post-training quantization). For higher precision (e.g., AF16), the impact is near-lossless (Morisaki, 26 Feb 2026).

7. Summary of Context and Applications

Lexicographic One’s-Complement Unpacking provides a deterministic, branchless mapping from raw codewords to lex-ordered signed integers and explicit floating-point fields. This technique enables block-scale-free inference datapaths, native integer comparability in floating-point hardware, and eliminates the need for hidden-bit or subnormal microcode. It has been uniquely adopted in the AetherFloat family as the foundation for both AF8 (QAT-first inference) and AF16 (bfloat16 replacement) formats. Its area, power, and latency reductions make it particularly suited for highly parallel AI accelerators in which datapath efficiency and deterministic timing are paramount (Morisaki, 26 Feb 2026).