Enriched 28Si Epilayers

• Isotopically enriched 28Si epilayers are high-purity silicon films engineered to minimize 29Si and 30Si contamination, thereby reducing electron spin decoherence.
• Advanced growth methods such as CVD, MBE, and high-fluence ion implantation with SPE enable precise control over layer thickness and crystalline quality.
• Comprehensive characterization using SIMS, APT, TEM, and RBS-C confirms the ultralow impurity levels and structural integrity needed for scalable quantum architectures.

Isotopically enriched $^{28}$Si epilayers are engineered silicon thin films with a highly purified $^{28}$Si isotope fraction, often used as host materials for spin qubits and quantum devices requiring a nuclear-spin-quiet environment. These epilayers are specifically designed to minimize the presence of $^{29}$Si, whose nuclear spin ($I=1/2$) leads to electronic spin decoherence, and $^{30}$Si, further reducing unwanted nuclear magnetic fluctuations. Techniques for producing such layers include chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and high-fluence $^{28}$Si$^-$ ion implantation with subsequent solid-phase epitaxy (SPE), yielding highly crystalline, thick ($\geq 100$ nm), and chemically pure $^{28}$Si films with residual $^{29}$Si concentrations reaching below 1 ppm (Lim et al., 4 Apr 2025, Mazzocchi et al., 2018, Holmes et al., 2020, Klos et al., 2024, Itoh et al., 2014).

1. Motivation and Physical Principles

The fundamental motivation for fabricating isotopically enriched $^{28}$Si epilayers stems from the suppression of electron spin decoherence in silicon-based quantum information platforms. Natural silicon consists of 92.23% $^{28}$Si (spin-0), 4.67% $^{29}$Si ($I=1/2$), and 3.1% $^{30}$Si (spin-0). The presence of $^{29}$Si nuclei introduces a dense nuclear spin bath, causing spectral diffusion and limiting the electron-spin coherence time $T_2$ in donor- and quantum dot-based qubits.

Empirical and theoretical studies demonstrate that the scaling of electron $T_2$ is approximately inversely proportional to the $^{29}$Si concentration $c_{29}$: $1 / T_2 \propto c_{29}$ Thus, orders-of-magnitude increases in $T_2$ are realized by reducing $c_{29}$ to ppm levels (Itoh et al., 2014). High-fidelity two-qubit gates, robust error correction, and fault-tolerant operation in silicon quantum processors all benefit directly from the "spin vacuum" provided by $^{28}$Si epilayers (Mazzocchi et al., 2018, Klos et al., 2024).

2. Methods of Enrichment and Epitaxial Growth

Several routes exist for the production of isotopically enriched $^{28}$Si epilayers. Primary methods include:

• Chemical Vapor Deposition (CVD): Using silane ($^{28}$SiH$_4$) precursors processed via centrifugal enrichment and employ ASM Epsilon 3200 tools for 300 mm wafers. Growth conditions: 650 °C, 20 Torr, linear growth rate $\approx$ 10 nm/min, yielding epilayers of 30–100 nm, with isotopic purities of $x_{28}>99.992$% ($^{29}$Si $< 0.005$%) (Mazzocchi et al., 2018).
• Molecular Beam Epitaxy (MBE): Utilizes $^{28}$Si evaporated from a high-purity source, optionally strained by SiGe buffers. Quantum well (QW) heterostructures are realized at substrate temperatures of $\sim 350$ °C, with deposition rates of 0.14 Å/s and residual $^{29}$Si content as low as 50 ppm (Klos et al., 2024).
• High-Fluence $^{28}$Si$^-$ Ion Implantation plus SPE: $^{28}$Si$^-$ ions are implanted into natural Si at energies (30–60 keV) and ultra-high fluences ($\Phi > 1\times 10^{18}\,\mathrm{cm}^{-2}$). Post-implantation annealing (SPE) at 620 °C for 10 minutes recrystallizes the amorphized region into a high-purity $^{28}$Si epilayer, achieving residual $^{29}$Si and $^{30}$Si below 1 ppm (measurement-limited) for layers $\geq 100$ nm thick (Lim et al., 4 Apr 2025, Holmes et al., 2020).

Method	Typical Layer Thickness (nm)	$^{29}$Si Concentration (ppm)	Key Process Variables
CVD	30–100	52 (SIMS-limited)	$^{28}$SiH$_4$ purity, 650 °C, 20 Torr
MBE	10–20	50	$^{28}$Si source purity, $T=350$ °C
Ion Implant.	$\geq$100	<1 (SIMS-limited)	$E_{\rm ion}=50$–60 keV, $\Phi > 0.6\times 10^{19}$ cm$^{-2}$, SPE 620 °C/10 min

3. Structural and Isotopic Characterization

Integrity, purity, and isotopic concentration in $^{28}$Si epilayers are established by several metrological techniques:

• Secondary Ion Mass Spectrometry (SIMS): Enables isotopic profiling with sub-ppm sensitivity; confirms monotonic $^{28}$Si dominance and low levels of $^{29}$Si/$^{30}$Si (Mazzocchi et al., 2018, Lim et al., 4 Apr 2025, Holmes et al., 2020).
• Atom Probe Tomography (APT): Provides atomically resolved isotope depth profiles, revealing interface structures, Ge segregation signatures (in SiGe heterostructures), and monolayer-scale compositional mixing (Klos et al., 2024).
• Transmission Electron Microscopy (TEM): Confirms single-crystal regrowth post-SPE; defect bands restricted to end-of-range depth ($\sim290$ nm for 45 keV) or absent in properly annealed samples (Holmes et al., 2020, Lim et al., 4 Apr 2025).
• Rutherford Backscattering/Channeling (RBS-C): Used for depth-resolved impurity and crystallinity analysis (Lim et al., 4 Apr 2025).
• Surface analysis (AFM, haze, particle counts): CVD-grown epilayers match or surpass micron-scale RMS roughness ($\sim$0.15 nm), haze, and particulate performance of standard CMOS silicon (Mazzocchi et al., 2018).

4. Annealing, Interface Engineering, and Impurity Control

Post-growth annealing is crucial for both epitaxial regrowth and property optimization:

• Solid Phase Epitaxy (SPE): Thermal sequences (e.g., 620 °C for 10 min in Ar) drive regrowth of amorphized, implanted layers into single-crystal $^{28}$Si with minimal EOR defects (Lim et al., 4 Apr 2025, Holmes et al., 2020). Rapid thermal anneal (1000 °C, 5 s) is employed for electrical activation of donors.
• Interfacial Segregation: In SiGe/$^{28}$Si/SiGe quantum wells, monolayer-scale Ge segregation at interfaces (2–3 ML width) is found by APT, and thermal annealing broadens only the top interface, directly affecting valley splitting (Klos et al., 2024).
• Impurity Management: Typical residual C and O concentrations in epilayers are $<10^{17}$ cm$^{-3}$, which does not impact spin coherence at donor densities used for qubits. TXRF measurements show total metallic contamination $<10^{10}$ atoms cm$^{-2}$ (Mazzocchi et al., 2018).

Step	Typical Parameter(s)	Effect on Epilayer
SPE	$T=620$\,$^\circ$C, $t=10$ min, Ar ambient	Single-crystal regrowth
Donor Activation	$T=1000$\,$^\circ$C, $t=5$ s, Ar rapid anneal	Electrical conductivity
Anneal (QW)	$T=700$\,$^\circ$C, $t=15$ s	Interface broadening (top)

5. Electronic and Coherence Properties

The degenerate electron bath of $^{28}$Si epilayers offers exceptional spin qubit performance:

• Electron Spin Coherence: Purified $^{28}$Si ($^{29}$Si$<250$ ppm) yields pulsed ESR Hahn-echo decay times $T_2=285\pm14\,\mu$s in phosphorus-implanted samples, exceeding natural-Si values at comparable donor concentration and limited primarily by instantaneous diffusion (Holmes et al., 2020). In QW devices with $^{29}$Si$=50$ ppm, $T_2^{\rm echo}=128$ μs; lower donor densities and further suppression of $^{29}$Si (below 1 ppm) are projected to extend $T_2$ to millisecond scales (Lim et al., 4 Apr 2025, Itoh et al., 2014).
• Valley Splitting: Large and uniform valley splitting values ($\Delta E_v \approx 200\,\mu$eV) in strained QWs with $<$1% Ge are observed, suppressing valley—scattering—a key decoherence pathway (Klos et al., 2024).
• Charge Noise and Mobility: Isotopic enrichment reduces low-frequency charge noise, yielding $>10^5$ cm$^2$/Vs electron mobilities and high-fidelity spin readout (Itoh et al., 2014).
• Device Compatibility: CMOS-foundry benchmarks (roughness, haze, particle levels, impurity thresholds) are met or exceeded, enabling integration into commercial 300 mm wafer lines (Mazzocchi et al., 2018).

6. Modeling and Predictive Control of Profiles

The design and optimization of $^{28}$Si epilayers employs predictive modeling:

• TRIDYN Binary-Collision Models: Used to simulate implantation depth, sputter yields, and isotope depletion profiles under varying fluence and energy. The evolution of $^{29}$Si concentration with fluence is captured by:

$$[^{29}\mathrm{Si}](\Phi) = [^{29}\mathrm{Si}]_{\rm nat} \exp\left(-\Phi/\Phi_0(E)\right)$$

with $\Phi_0(E)$ extracted by fitting to SIMS and TEM data (Lim et al., 4 Apr 2025).

• Valley Splitting Modeling: Tight-binding computational frameworks, seeded by atomically resolved Ge depth profiles, predict the probability distribution of valley splitting and its enhancement due to minimal, well-positioned Ge incorporation at the monolayer scale (Klos et al., 2024).

7. Scalability, Integration, and Outlook

$^{28}$Si epilayers are demonstrated on full 300 mm wafers with isotopic, chemical, and crystalline purity on par with state-of-the-art CMOS standards (Mazzocchi et al., 2018). Process windows for high-temperature steps are defined by isotopic diffusion coefficients ($D_{\rm Si}^{\rm SD}(T)$), with $<$2 min at 925°C preserving sharp $^{28}$Si/nat-Si interfaces. CVD, MBE, and ion-implant processes are largely transferrable to existing foundry lines. Remaining challenges include scaling the supply of high-purity $^{28}$SiH$_4$ feedstock, maintaining impurity exclusion through back-end processing, and consistent mitigation of point defects and threading dislocations in SOI and heterostructure contexts (Lim et al., 4 Apr 2025, Itoh et al., 2014). The convergence of isotopic purification, defect-free epitaxy, and reliable interface engineering positions $^{28}$Si epilayers as the preeminent platform for scalable, high-fidelity silicon spin quantum architectures.