Hybrid Solvers for Combinatorial Optimization

• Hybrid solvers are computational frameworks that combine classical CPUs with specialized hardware to decompose and solve large combinatorial challenges.
• They employ decomposition techniques like k-core analysis and QUBO formulations to allocate subproblems efficiently while reducing overhead and data transfer costs.
• These approaches enable significant runtime improvements in real-world applications such as logistics, scheduling, and portfolio optimization.

Hybrid solvers for combinatorial optimization are computational architectures and algorithms that integrate diverse types of hardware—typically general-purpose CPUs and specialized non-CPU devices such as FPGAs, ASIC-based annealers, or quantum processors—to efficiently solve large and complex combinatorial problems. These approaches combine the flexibility and broad applicability of classical computing with the speed or specialized capabilities of emerging hardware for subproblems that fit certain structural or size constraints. The essential insight is that partitioning combinatorial problems into parts tractable for specialized devices, while handling the remainder with classical methods, enables the practical treatment of problems that are otherwise computationally intractable.

1. Hybrid System Architecture and Decomposition Principles

Hybrid combinatorial solvers are architected around a division of labor between classical and non-classical computational resources. The total computation time is modeled as

$$T_{\text{total}} = t_{\text{CPU}} + t_{\text{comm}} + t_{\text{non-CPU}},$$

where $t_{\text{CPU}}$ encompasses classical tasks such as preprocessing, problem decomposition, and postprocessing; $t_{\text{comm}}$ is the time for data transfer and communication between hardware modules; and $t_{\text{non-CPU}}$ is the duration spent on the special-purpose device (Narimani et al., 2017). The key to efficient hybrid solving is to minimize overhead while maximizing the acceleration obtained from specialized hardware on subproblems it is well equipped to solve.

The central methodological underpinning is decomposition: large combinatorial problems are recursively split into smaller subproblems. These are assigned based on suitability and hardware constraints to either CPUs or non-CPU components. Simple delegation sends problems directly to non-CPU hardware when possible; iterative decomposition continues splitting until all subproblems fit resource limits; and hybrid decomposition with decision-making uses bounds and instance-specific criteria to dynamically allocate subproblems, thereby reducing unnecessary hardware calls.

2. Algorithms, Decomposition Techniques, and Subproblem Assignment

An effective decomposition workflow for hybrid solvers involves:

1. Testing well-suitedness and size: If a subproblem is not compatible with the target hardware or is too large, further decomposition is applied. Otherwise, it is assigned appropriately.
2. Bound-based routing: For each subproblem, upper (for maximization) or lower (for minimization) bounds are estimated. A decision module assigns the subproblem to the non-CPU device if running it is likely to be advantageous, otherwise to the CPU.
3. Subproblem packing and pruning: Routines such as “PruneAndPack” minimize the communication overhead by aggregating or batching similar subproblems.
4. Result aggregation: After both CPU and non-CPU tasks complete, their partial results are combined for the final solution.

Pseudocode abstraction:

Procedure Decompose(problem, nonCPU_size, decomposition_level): if not well_suited(problem): solve_on_CPU(problem) elif problem_size < nonCPU_size: solve_on_nonCPU(problem) else: subproblems = decompose(problem) for subproblem in subproblems: if not well_suited(subproblem): add_to_CPU_queue(subproblem) elif subproblem_size > nonCPU_size: further_decompose(subproblem) else: add_to_nonCPU_queue(subproblem) PruneAndPack(subproblems) Aggregate(results_from_CPU_and_nonCPU)

(Narimani et al., 2017)

This workflow ensures that the decomposition and scheduling of subproblems scale polynomially and that overall runtime gains are possible whenever the assigned hardware achieves a substantial speedup per call.

3. Specialized Hardware Roles and Problem Formulations

FPGA and ASIC-based digital annealers, as well as quantum processors like the D-Wave 2000Q, are leveraged for those subproblems that fit their restrictive resource and connectivity profiles. Crucial to this integration is the formulation of subproblems in QUBO or related forms. For example, quantum and digital annealers can efficiently solve QUBO-encoded problems within their hardware limits, often in highly parallelized fashion.

Quantum processors, despite small logical capacities, can be effectively utilized for complex instances by mapping large problems into a collection of small QUBO problems. Effective translation to the hardware-specific format—while considering overheads in data transfer and the cost of preparing/reading hardware—is key to obtaining net computational benefit.

4. Maximum Clique and k-Core Decomposition: Industrial Case Study

The maximum clique problem, an NP-hard task requiring the identification of the largest complete subgraph in a given graph $G = (V, E)$, exemplifies scalable hybrid solving via problem-specific decomposition (Narimani et al., 2017). A k-core decomposition technique is used:

• Each vertex $v$ is assigned a core number $K(v)$, the largest $k$ such that $v$ is in the $k$-core.
• Vertices are ordered by degeneracy.
• The problem can be split into at most $n - K(G) + 1$ subproblems of size at most $K(G)$, where $n = |V|$, $K(G)$ is the max core number, and

$\omega(G) \leq K(G) + 1 \leq \Delta(G) + 1$

with $\omega(G)$ the clique number and $\Delta(G)$ the maximum degree.

On large, sparse graphs (e.g., the com-Amazon graph with 334,863 vertices and nearly 1 million edges), the k-core number is small (e.g., $K(G)=6$), enabling decomposition into manageable subproblems—often just a handful—solvable with a non-CPU device that can only embed small graphs. This dramatically reduces computational and memory requirements and allows integration with classical solvers for post-processing or verification.

5. Performance, Scalability, and Industrial Implications

Hybrid architectures make it feasible to tackle very large and complex combinatorial problems by exploiting the speed of specialized non-CPU devices on properly structured subinstances while leaving the remainder to CPU-based code. For example, the k-core decomposition drastically reduces problem size for large, sparse graphs and can improve the runtime of established algorithms such as PMC and BBMCSP by orders of magnitude. However, in dense graphs where k-core numbers are higher, several decomposition levels or advanced bounding heuristics (e.g., DSATUR for graph coloring) may be necessary.

In real-world industrial settings (such as logistics, scheduling, and portfolio optimization), this methodology enables the practical application of hybrid solvers to data sizes that would otherwise be out of reach. Potential challenges include the management of overhead due to subproblem formatting and data transfer, especially when many subproblems are generated.

A key advantage is that even small or limited non-CPU hardware can be competitive when mass-produced, highly parallelized, or capable of solving specific small subproblems significantly faster than CPUs—shifting the cost-benefit profile in favor of hybrid architectures.

6. Limitations, Overheads, and Future Perspectives

Critical to the effectiveness of hybrid combinatorial solvers are the following challenges:

• Overhead management: Problem decomposition, QUBO conversion, and data marshaling must be efficient enough not to erase the speedup provided by hardware acceleration.
• Communication costs: Minimizing $t_{\text{comm}}$ is essential, particularly with large quantities of small subproblems.
• Structural dependence: The benefit of decomposition is highly dependent on the input problem’s structure; sparse problems lead to dramatic reductions, while dense problems may require multi-level decompositions.
• Hardware parallelization: Achieving the full benefits often requires cheap and massive parallelization or customization in hardware.

These limitations motivate further research into decomposition-aware scheduling, advanced subproblem packing, and efficient formats for hardware interoperability.

7. Theoretical and Methodological Advances

The hybrid approach lays clear algorithmic foundations for further development: clear decomposition and assignment strategies, formal performance bounds (e.g., scaling of subproblem counts), and integration routines. These foundations facilitate both the construction of new hybrid architectures and the adaptation of emerging hardware to optimization tasks, supporting further progress in large-scale industrial combinatorial optimization.

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Hybrid solvers for combinatorial optimization constitute a versatile and scalable architectural paradigm. By decomposing problems and judiciously assigning subproblems to conventional and specialized hardware, they overcome hardware resource limitations, deliver substantial runtime improvements, and enable complex industrial problem solving (Narimani et al., 2017). This approach, with provable algorithmic bounds and demonstrated practical success, forms a robust template for continued advances in both theoretical and applied combinatorial optimization.