Hardware-Algorithm Co-Design Framework

• Hardware-algorithm co-design framework is a unified method combining algorithm design with hardware implementation through normalized, multi-profile performance indicators.
• It employs a structured benchmarking process with profiles such as GAP, SWP, and HWP to optimize resource allocation and algorithm-hardware partitioning.
• The framework facilitates transparent trade-off evaluations across platforms by leveraging geometric means and weighted metrics for actionable design choices.

A hardware-algorithm co-design framework is a methodological paradigm for integrating algorithmic design and hardware implementation through a unified, quantitative performance analysis process. Its purpose is to optimize algorithm selection, configuration, and partitioning according to the heterogeneous characteristics and constraints of hardware and software targets. The central concept, as formalized by Damaj & Kasbah, is to leverage normalized, multi-profile performance indicators—such as throughput, area, power, latency, and algorithmic complexity—to rank and classify candidate algorithms across diverse platforms using geometric means and weighted compositions of such measures (Damaj et al., 2019). The framework is highly customizable and statistically grounded, supporting actionable decisions on algorithm-hardware partitioning, resource allocation, and system deployment.

1. Formal Structure and Key Performance Indicators

The framework is defined over a set of algorithms $A = \{ a_1, a_2, \ldots, a_M \}$, contrasted against a reference algorithm $a_{ref} \in A$ for normalization. Analysis Profiles $J = \{ 1, \ldots, P \}$ group key indicators (KIs) by domain: algorithmic (GAP), software (SWP), hardware (HWP), or additional profiles as needed (e.g., GPU, DSP, I/O).

Within each profile $j$, raw metrics $KI_{i,j}(a)$ for $a \in A$ are normalized into dimensionless ratios:

• If "larger is better": $r_{i,j}(a) = KI_{i,j}(a) / KI_{i,j}(a_{ref})$
• If "smaller is better": $r_{i,j}(a) = KI_{i,j}(a_{ref}) / KI_{i,j}(a)$

Profile-level Combined Measurement Indicators (CMIs) are formed by the geometric mean:

$$CMI_j(a) = \left( \prod_{i=1}^{n_j} r_{i,j}(a) \right)^{1/n_j}$$

Overall indicators—for example, the "Lightness Indicator" (LI)—combine multiple profiles:

$$LI(a) = \left( \prod_{k=1}^{L} r_{k}(a) \right)^{1/L}$$

Weighted versions allow the relative importance of each KI:

$a_{ref} \in A$0

This formalism supports the flexible addition, removal, and weighting of indicators to match any hardware-algorithm scenario.

2. Methodology for Contextualization and Customization

The co-design workflow proceeds as follows:

1. Platform Selection: Choose the processing environments and devices (multi-core CPU, FPGA, GPU, etc.).
2. Profile & KI Definition: Establish analysis profiles with relevant KIs—both quantitative (e.g., LUT count, execution time, throughput) and qualitative (e.g., security class mapped to numerics).
3. Reference Choice: Select a baseline algorithm $a_{ref} \in A$1 for normalization.
4. Data Collection: Implement each algorithm in each environment; measure all KIs.
5. Normalization: Convert KIs to ratios $a_{ref} \in A$2, standardizing directionality of "goodness."
6. Indicator Combination: Aggregate KIs into CMIs using the geometric mean formulas; apply weights as needed.
7. Ranking/Classification: Sort algorithms by CMI or LI values for decision support.

Qualitative KIs are mapped to numbers using fixed rubrics, facilitating their integration into the overall statistical framework.

3. Case Study: Lightness Indicator System (LIS) in Cryptography

The LIS instantiates the framework for lightweight cryptographic cipher evaluation:

• General Algorithmic Profile (GAP): AC (complexity), KS (key size), NR (rounds), BS (block size)
• Software Profile (SWP): ET_sw (execution time), TH_sw (throughput), CPI, CMR (cache miss rate)
• Hardware Profile (HWP): ET_hw, TH_hw, PD (propagation delay), LUT, LR (registers), PC (power)

Combined indicators are constructed for complexity (CI), security strength (SSI), hardware lightness (HLI), software lightness (SLI), and speed (SI), each as a geometric mean over relevant KI ratios with AES as the reference.

For ten ciphers, the LIS classified 3-WAY as highest (LI ≈ 2.52), HIGHT second (1.93), KATAN-64 lowest (0.76), confirming fine-grained distinctions across hardware and software modalities.

Cipher	LI	HLI	SLI	CI	SSI	SI
3-WAY	2.52	3.12	2.44	1.45	1.44	2.44
HIGHT	1.93	2.21	1.98	1.41	1.41	1.77
KATAN-64	0.76	0.74	0.80	0.94	0.96	0.82

Evaluation revealed trade-offs visible only through parallelized indicator inspection—e.g., 3-WAY is hardware-compact but less efficient in software, while others are reversed.

4. Benchmarking Model and Decision Guidance

A generic benchmarking analysis using this framework comprises:

1. Goal: Specify the comparative purpose (e.g., "select the lowest-power cipher for an FPGA").
2. Inputs: List algorithms, platforms, reference, and chosen metrics.
3. Data Generation: Create implementations, automate measurements, and tabulate raw KI values.
4. Indicator Table: Output normalized ratio and rubric mappings.
5. Indicator Calculation: Compute profile CMIs and overall indicators.
6. Outcomes: Produce ranked tables and charts for classification.

This process is readily adaptable (via spreadsheet, script, or toolbox integration) and supports rapid iteration and visualization of the co-design space.

5. Design Trade-offs and Decision Guidelines

Inspection of profile indicators uncovers actionable hardware–software trade-offs:

• Functional Coverage: The framework ensures no critical security or algorithmic property is compromised for lightweight implementation.
• Domain Suitability: Some ciphers show extreme hardware compactness (e.g., 3-WAY at 77 ALUTs), but weaker software metrics, guiding algorithm choice for hybrid deployments.
• Indicator Guidance: The speed indicator amalgamates software and hardware speed, providing a direct metric for real-time or high-throughput scenarios.
• Partitioning Decisions: By examining CMIs, designers can repartition algorithm components across hardware and software as needed to optimize targeted indicators.

The CMI-driven ranking approach replaces arbitrary, platform-specific tuning with transparent, statistically grounded design choices.

6. Application to General Co-Design Scenarios

For arbitrary hardware-algorithm co-design tasks:

• Define the candidate algorithm set and reference.
• Specify all target platforms and devices.
• Tailor the profile/KI set to the application domain.
• Implement and measure, normalize, group, and compute ratios.
• Aggregate into CMIs and rank.

The geometric mean machinery supports seamless extension to new domains, rubrics, and metrics, maintaining methodological rigor without redesign of the analysis engine.

7. Framework Generalization and Impact

The Damaj & Kasbah framework offers a statistically unified and contextually flexible method to fuse heterogeneous hardware and software metrics into low-dimensional, actionable indicators. Its reliance on geometric means of normalized ratios ensures resilience to scale, distribution, and metric directionality, supporting transparent comparison across platforms and applications.

This architecture enables both rapid benchmarking and systematic co-design for robotics, embedded systems, cryptography, signal processing, and beyond, and is extensible to emerging performance domains—energy, reliability, accuracy, I/O bandwidth, and more—through profile and KI customization (Damaj et al., 2019).