Hardware-Affinity Workload Mapping

• Hardware-affinity workload mapping is defined as the systematic assignment of computational tasks to hardware resources to optimize performance, energy, and thermal profiles.
• It employs detailed profiling, affinity matrices, and diverse heuristic algorithms to tackle challenges across HPC, AI accelerators, neuromorphic, and quantum systems.
• Practical implementations have demonstrated significant improvements in throughput, energy savings, and reduced communication costs in large-scale and heterogeneous compute environments.

Hardware-affinity workload mapping refers to the systematic assignment of computational tasks, code segments, or application subcomponents to physical hardware resources such that the “fit” between workload characteristics and hardware capabilities (or limitations) is explicitly exploited. The notion of affinity encompasses not only maximal utilization and performance but frequently extends to minimizing power, communication, or wear-out/thermal gradients by leveraging detailed knowledge of the device, topology, and technology. Hardware-affinity mapping has emerged as a central challenge in modern HPC, accelerator, neuromorphic, AI, and even quantum systems, owing to the increasing heterogeneity and architectural complexity of large-scale compute fabrics.

1. Theoretical Foundation of Hardware-Affinity Mapping

Hardware affinity is formally modeled through affinity matrices, cost functions, and system-specific constraints. Classic definitions assign an affinity score $A_{ij}$ to each (task $i$, resource $j$) pair, quantifying the suitability according to workload profile (compute, memory, I/O demand) and resource vector (e.g., compute rate $R_j$, memory size $M_j$, device-specific features) (Sharma et al., 16 May 2025).

The general mapping problem is combinatorial, with formalizations including:

• Assignment variable: $x_{ij} \in \{0,1\}$, where $x_{ij}=1$ iff task $i$ is mapped to resource $j$.
• Objective functions: minimizing makespan ($C_{\max}$), load variance, or total energy, usually subject to per-resource capacity and affinity constraints:

$$\min_{x}\; C_{\max} = \max_{j}\left\{\sum_{i}p_i x_{ij}\right\}$$

$x_{ij} \leq \mathbb{1}_{A_{ij} \geq \alpha}$

Hybrid and multi-objective formulations minimize multiple cost elements (latency, energy, area) as in chiplet-based accelerator mapping (Das et al., 2022).

Workload profiling (FLOPS, memory, comm), affinity modeling, mapping/scheduling, and execution/feedback form the canonical workflow (Sharma et al., 16 May 2025).

2. Affinity Metrics and Workload Profiling Techniques

Affinity mapping relies on extracting precise metrics from both the workload and hardware. Typical features used:

• Per-task demand vectors: compute intensity, memory footprint, communication volume.
• Microarchitectural counters: e.g., IPC, cache misses, DRAM traffic (Shubham et al., 2024).
• Workload segments: for SNNs/ANNs, these are clusters of neurons/synapses; for distributed HPC, graph partitions; for RL pipelines, trajectories tagged by compute/bw/stateful profile (Gao et al., 27 Dec 2025).

In neuromorphic hardware, mapping leverages cell-level details such as bitline current, phase-change cell resistance, and temperature spatial coupling (Titirsha et al., 2020). In memory-centric systems (ALP), data movement patterns and segment “connectivity” are profiled using liveness and inter-segment register overlap (Ghiasi et al., 2022).

In quantum systems, region selection is guided by hardware-induced fidelity metrics, quantifying two-qubit gate errors and community modularity (Sun et al., 23 Apr 2025).

Table: Affinity Metrics by System Domain

Domain	Affinity Metric(s)	Profiling Tools
HPC/Cloud	$A_{ij}$, job power, runtime, energy	HW counters, predictive models
Neuromorphic	Cell temperature, bitline location, endurance	Circuit/thermal simulation
AI Accelerators	Resource slices, bandwidth, compute units	Compiler IR, runtime statistics
Quantum	Edge/region fidelity, modularity	Hardware calibration data
RL/LLM Disagg.	Prefill/decode time ratio, task tag	Micro-benchmarking, tracing

3. Mapping Algorithms and Heuristic Strategies

Mapping involves solving (often NP-hard) optimization problems under affinity, capacity, and communication constraints.

• Greedy heuristics: Assign highest-affinity task–resource pairs first (Affinity-First) (Sharma et al., 16 May 2025, Sharma et al., 18 May 2025). List scheduling and upward-rank orderings are used in practical systems.
• Graph-based partitioning: Kernighan–Lin, hierarchical multisection, and local refinement for process mapping across hardware trees (Titirsha et al., 2021, Schulz et al., 2 Apr 2025).
• Meta-heuristics: Genetic algorithms, Particle Swarm Optimization (PSO), Simulated Annealing (SA); often customized for heterogeneity and objective mixes (e.g., MOHaM (Das et al., 2022)).
• MILP/ILP: For small problem sizes, optimal assignment with formal cost embedding; LP relaxations for larger settings (Sharma et al., 18 May 2025).
• Machine Learning: Hardware counter-driven ML models (e.g., XGBoost for vector supercomputer interference) (Shubham et al., 2024).
• Custom heuristics: Hill climbing for minimizing thermal gradients in neuromorphic crossbars (Titirsha et al., 2020), “hw_mapping” decorators for RL pipelines (Gao et al., 27 Dec 2025).
• Hybrid approaches: Combine fast greedy with MILP or meta-heuristics and, in nascent work, quantum annealing for combinatorial optimization (Sharma et al., 16 May 2025).

For agentic RL and edge/cloud continuum, mapping also exploits runtime resource labels, tagging, and task-class based policies (Gao et al., 27 Dec 2025, Sharma et al., 18 May 2025).

4. System-specific Approaches and Case Studies

Distinct mapping methodologies have been designed for various architectures.

• Neuromorphic hardware: DFSynthesizer pipelines SNN partitioning, spatial decomposition, and SDFG-based mapping to crossbar arrays subject to buffer and bandwidth constraints, yielding $\sim$15–40% throughput gains (Song et al., 2021). Thermal-aware mappers model spatial temperature distribution and steer hot synapses to cooler regions, halving leakage power (Titirsha et al., 2020). Endurance-aware mapping uses activation frequency and cell-level endurance maps to maximize minimum device lifespan (Titirsha et al., 2021).
• CGRAs: Abstractions such as resource “slices” (GLB, bandwidth, PEs) enable compile-time variant generation and runtime slice assignment, with dynamic partial reconfiguration (DPR) for multi-task deployment (Kong et al., 2023).
• Quantum mapping: HAQA accelerates solver-based mapping by community-based region identification and fidelity-aware region selection, achieving over $100\times$ speedup and up to 2–3$\times$ fidelity improvements for IBM Eagle/Heron (Sun et al., 23 Apr 2025).
• Agentic RL and LLM training: RollArt dynamically routes trajectories based on compute/bw/stateful profiles to GPU/CPU/serverless backends, using per-invocation O($W$) affinity filtering and tag-based resource allocation (Gao et al., 27 Dec 2025).
• Shared-memory supercomputing: Multilevel graph partitioning matches hierarchical hardware for optimal data locality and minimal communication (Schulz et al., 2 Apr 2025).
• Multi-DNN on chiplets: MOHaM co-optimizes SAI selection/configuration, layer mapping, and NoP placement under multi-objective constraints, using NSGA-II with problem-specific genetic operators (Das et al., 2022).
• HPC scheduling: EAMC and related Slurm plugins use regression-based hardware/job models to favor assignments that minimize energy and response time across clusters and DVFS states (D'Amico et al., 2021).

5. Quantitative Impact and Experimental Evidence

Hardware-affinity mapping consistently improves core efficiency, energy profile, communication cost, thermal stress, and workload turnaround.

• In neuromorphic mapping, $11.4\,\mathrm{K}$ per-tile average temperature drop and $52\%$ leakage reduction were demonstrated (Titirsha et al., 2020).
• In quantum mapping, fidelity boosts of up to 238% and $>100\times$ reduction in mapping time are reported (Sun et al., 23 Apr 2025).
• RollArt’s mapping increased RL rollout throughput by $1.30-1.68\times$ and delivered $2.05\times$ end-to-end speedup on production clusters (Gao et al., 27 Dec 2025).
• SharedMap (hier. multisection) achieved the best mean comm. cost on 95% of large-scale graph benchmarks, while being $1.04\times$ faster than the next-best (Schulz et al., 2 Apr 2025).
• In CGRAs, flexible-shape mapping yielded $23-28\%$ latency reduction and up to $1.24\times$ throughput gain (Kong et al., 2023).
• Meta-studies of heterogeneous HPC show median makespan reductions of 35% and energy savings up to 50% with heuristics/meta-heuristics over baselines (Sharma et al., 16 May 2025).

Table: Representative Improvement Metrics

System/Workload	Metric	Affinity Mapping Result	Reference
Neuromorphic SNN	Leakage power	$-52\%$ vs. baseline	(Titirsha et al., 2020)
Quantum IBM Eagle	Mapping runtime	$>100\times$ speedup	(Sun et al., 23 Apr 2025)
RL LLM, RollArt	Throughput	$1.68\times$ improvement	(Gao et al., 27 Dec 2025)
HPC Process Mapping	Communication cost	Best on 95%, runtime 1.04$\times$ faster	(Schulz et al., 2 Apr 2025)
CGRA Multi-task	Throughput	$1.24\times$ improvement	(Kong et al., 2023)

6. Practical Challenges, Limitations, and Directions

Despite rich algorithmic and experimental progress, several open problems persist.

• Problem scale: MILP/ILP solvers become intractable for large $n,m$; heuristics and meta-heuristics are standard, but their solution quality can be $\sim$5–10% suboptimal (Sharma et al., 18 May 2025).
• Dynamic affinity: Runtime-reconfigurable systems require dynamic affinity estimation and (re-)mapping, an area with limited robust solutions (Sharma et al., 16 May 2025).
• Heterogeneity modeling: Many frameworks (e.g., CGRA slice abstractions) assume homogeneous slices; supporting heterogeneity at the micro-architecture level complicates modeling (Kong et al., 2023).
• Integration with scheduling infrastructure: Plugins for schedulers (e.g., Slurm EAMC) are needed for seamless deployment, but must be extended for GPUs/AI accelerators (D'Amico et al., 2021).
• Complex workloads: Compositional and stateful workloads (agentic RL, multi-DNN inference) require custom tagging and segmentation; automating tag/class inference and migration is an active direction (Gao et al., 27 Dec 2025).
• Tool support and benchmarking: Formalization of standardized benchmarking and integration with toolchains (CloudSim, CPLEX, Ray, Timeloop/Accelergy, D-Wave) is ongoing (Sharma et al., 16 May 2025, Das et al., 2022).

Key opportunities include hybrid meta-ILP and RL scheduling, quantum-inspired optimization for mapping sub-problems, and deeper fusion of profiling, ML affinity inference, and dynamic context tracking.

7. Design Principles and Guidelines

Core principles emerging across research include:

• Model both static and dynamic affinity—compute, memory, communication, thermal, wear, and interference all matter in different settings (Titirsha et al., 2020, Shubham et al., 2024, Titirsha et al., 2021).
• Use affinity metrics to prune mapping space: early-discards and region reduction (HAQA, tag-based filters).
• Exploit hardware topology and constraints explicitly: e.g., multisection by hierarchy, chiplet placement, slice-based abstractions.
• **Prefer locally optimal but scalable heuristics/GA for large-scale systems, fallback to global optimal solvers for small/high-value workflows (Sharma et al., 18 May 2025, Das et al., 2022).
• Integrate with runtime and tool ecosystem: via plugin frameworks, API-based schedulers, and standard simulation/solver tool support.
• Iterative feedback: Profile–Map–Monitor–Refine as the default mapping lifecycle.

Hardware-affinity workload mapping is now foundational for scalable, efficient, and robust scheduling and deployment in next-generation computing systems, with cross-domain algorithmic and systems research setting its core methodologies and practical impact.