GRAPHIC: In-SSD Graph Computing for Large-Scale GNNs

• GRAPHIC is an in-SSD graph computing system that offloads irregular aggregation to storage, mitigating SSD-to-DRAM bottlenecks in large-scale GNN workloads.
• CGTrans performs semantic compression by aggregating neighbor features in-SSD, reducing data movement from O(k) per seed node to a single compact aggregate.
• FAST-GAS enables high-concurrency gather-and-scatter inside SSD, leveraging CAM and FAST-SRAM to boost area efficiency and overall throughput.

GRAPHIC is an in-SSD graph computing system for very large-scale graph convolutional workloads in which aggregation is moved from the host side into the SSD, and only compact per-node aggregates are transmitted to the host accelerator. It combines Compressive Graph Transmission (CGTrans) with the FAST-GAS in-SSD accelerator so that the irregular, memory-bound aggregation phase of GCN and GraphSAGE executes near the graph data, while the regular combination MLP remains on a host PE array. The system is motivated by the observation that, at terabyte-scale graph sizes, SSD-to-DRAM movement rather than DRAM traffic becomes the dominant latency bottleneck; experimentally, CGTrans reduces SSD loading by approximately $50\times$, and the full GRAPHIC system achieves $3.6\times$ average speedup over GCNAX and $2.4\times$ average speedup over CGTrans on Insider (Chen et al., 2022).

1. SSD-resident graph data as the dominant systems bottleneck

GRAPHIC targets the execution regime in which graph neural network inference, and potentially training, operates over graphs with hundreds of millions of nodes and billions of edges, yielding an overall working set at terabyte scale. In that setting, graph data cannot fit into DRAM, so edge lists and node features must reside in SSD and repeatedly traverse the SSD–host path. Prior ASIC accelerators such as GCNAX reduce DRAM accesses by up to $8\times$ over earlier designs, but they still assume that sparse features and edges can be supplied from SSD fast enough; GRAPHIC is designed precisely for the regime in which that assumption breaks down (Chen et al., 2022).

The underlying workload structure is the standard separation between an irregular aggregation phase and a regular, compute-intensive combination phase. In a Kipf–Welling GCN layer,

$$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$

the accelerated term is

$$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$

For GraphSAGE-style execution with fixed fanout $k$,

$$m_v^{(l)} = AGGREGATE(\{ h_u^{(l)} : u \in N_k(v) \}),$$

followed by a host-side combination such as

$$h_v^{(l+1)} = \sigma\!\left(W^{(l)} \cdot [ h_v^{(l)} \,||\, m_v^{(l)} ]\right),$$

or a reduced variant without concatenation. GRAPHIC leaves the dense host-side combination intact and relocates the irregular $AGGREGATE$ stage into SSD (Chen et al., 2022).

This division is significant because aggregation requires random access to a large set of neighbor features. Once the graph exceeds memory capacity, SSD loading latency and SSD I/O bandwidth dominate end-to-end latency. A plausible implication is that DRAM-centric accelerator optimizations alone cease to determine system throughput once the storage hierarchy becomes the true limiter.

2. CGTrans: semantic compression by in-SSD aggregation

CGTrans, or Compressive Graph Transmission, is the core dataflow transformation in GRAPHIC. Its principle is not entropy coding but semantic compaction by reduction: the SSD performs neighbor lookup and aggregation in situ, and transmits only the aggregated feature vector for each seed node rather than the $3.6\times$0 neighbor feature vectors required by host-side aggregation. In GraphSAGE-style inference, this changes many-to-one traffic into one-to-one traffic (Chen et al., 2022).

Ignoring metadata and control overheads, the conventional host-side flow moves approximately

$3.6\times$1

where $3.6\times$2 is the number of sampled seed nodes, $3.6\times$3 is the number of sampled neighbors per seed, $3.6\times$4 is the feature dimension before aggregation, and $3.6\times$5 is bytes per feature element. With CGTrans, the SSD sends only one aggregated feature per seed node:

$3.6\times$6

The resulting compression ratio, equivalently the SSD load reduction factor, is

$3.6\times$7

For GraphSAGE with $3.6\times$8, the expected reduction is therefore approximately $3.6\times$9, matching the reported average SSD loading reduction (Chen et al., 2022).

The execution flow is correspondingly altered. In the baseline, the host samples seeds, loads neighbor IDs and features from SSD to DRAM, performs aggregation on the host accelerator, then applies the MLP. Under CGTrans, seeds and sampling parameters are sent to the SSD; the SSD performs sparse neighbor lookup and reduction; only $2.4\times$0 is transmitted to host DRAM; the host PE array computes the dense transformation $2.4\times$1; the activation is applied; and updated node features are written back to SSD. This suggests that CGTrans is best understood as a bandwidth rebalancing mechanism: it substitutes relatively cheap reduction near storage for expensive transport of raw sparse neighborhoods.

3. FAST-GAS: high-concurrency gather-and-scatter inside SSD

GRAPHIC depends on an in-SSD accelerator named FAST-GAS, built from the Fully Concurrent Access Technique (FAST). FAST SRAM introduces per-row cyclic shift capability using controlled inverter loops, so that each row can shift its word independently and concurrently with other rows. A 1-bit ALU per row supports bit-serial arithmetic such as add, min, and max; multibit operations are constructed from sequences of 1-bit steps. The design goal is high in-place parallelism with strong area efficiency (Chen et al., 2022).

The GAS engine integrates three structures. A CAM stores edge endpoints in COO format and provides massively parallel associative lookup. FAST SRAM stores feature rows aligned with CAM entries and performs in-place bit-serial aggregation. A lightweight 1-bit SFU assists with row reduction, including adder-tree support for sum and min/max operations. The central coupling is that CAM match lines directly gate the corresponding FAST-SRAM rows, so matched rows operate while unmatched rows remain idle. This avoids a large CAM priority decoder and enables high match concurrency. Idle-skip buffers further increase effective utilization under sparsity by skipping cycles with no CAM match (Chen et al., 2022).

Concurrency exists at two levels. At row level, all matched rows in a FAST-SRAM array can operate in parallel in a cycle; the circuit-level evaluation uses a $2.4\times$2 array. At array level, multiple GAS arrays can be instantiated to exploit SSD internal parallelism across channels and dies. GRAPHIC places FAST-GAS in the SSD cache path under a FAST-GAS controller, replacing a conventional read/write cache with an aggregation-capable storage-side compute substrate (Chen et al., 2022).

Circuit-level evaluation reports the following costs for the evaluated $2.4\times$3 arrays:

Component	Area	Energy / latency
FAST-SRAM	$2.4\times$4	$2.4\times$5 per 16-bit add+writeback; $2.4\times$6
CAM	$2.4\times$7	$2.4\times$8 add-path overhead; $2.4\times$9

Against Insider, the FPGA-in-SSD near-storage system used as a comparison point, FAST-GAS is reported to provide approximately $8\times$0 area-efficiency improvement for aggregation. A plausible implication is that CGTrans only becomes practically attractive when the storage-side reduction engine is itself area-normalized enough not to collapse throughput.

4. End-to-end system organization and execution model

The GRAPHIC system comprises an SSD augmented with FAST-GAS and a FAST-GAS controller, a host with DRAM, and a PE array for the dense combination stage. The graph resides in SSD in COO form for edges and aligned feature storage for node data. For GCN and GraphSAGE, gather and reduce occur in SSD; the host performs the MLP; updated features are written back to SSD. The system pipelines batches so that SSD-side aggregation for batch $8\times$1 overlaps with host-side combination for batch $8\times$2 (Chen et al., 2022).

Storage organization is explicit. Each CAM row stores $8\times$3 for one edge in COO format. The corresponding FAST-SRAM row stores the source feature vector, or the value required by the current phase. An alternative dense-bitmap mode is available for certain aggregations, where columns of the conceptual adjacency matrix activate rows in FAST-SRAM; the matrix is generated on the fly rather than stored densely. Aggregation for each destination $8\times$4 reduces across all matched rows $8\times$5, and the result $8\times$6 is emitted atomically before moving to the next seed. For scatter/writeback algorithms such as SSSP, row content is updated in situ after each atomic operation (Chen et al., 2022).

The latency model makes the design rationale explicit. In a baseline host-side flow,

$8\times$7

For GRAPHIC,

$8\times$8

The speedup is

$8\times$9

The decisive change is that $$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$0 and $$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$1 are removed as separate host-visible stages, while $$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$2 is reduced by approximately $$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$3. Although in-SSD aggregation is slower than a large host ASIC in absolute compute terms, it executes behind the SSD interface and can be overlapped with the host MLP, so end-to-end behavior is dominated by the I/O reduction rather than raw arithmetic speed (Chen et al., 2022).

5. Workloads, datasets, and reported performance

The primary GCN workload used for evaluation is GraphSAGE inference with first-layer sampling at $$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$4 neighbors per seed node. Reported datasets include Reddit ($$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$5 million nodes, $$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$6 billion edges), Movielens ($$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$7 million nodes, $$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$8 billion edges), Amazon ($$H^{(l+1)} = \sigma\!\left(\tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)} W^{(l)}\right),$$9 million nodes, $$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$0 billion edges), OGBN-100M ($$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$1 million nodes, $$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$2 billion edges), and Protein-PI ($$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$3 million nodes, $$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$4 billion edges). The system is also evaluated on Feature Embedding, BFS, SSSP, CC, and Sort, with GAS cache sizes of 128 KB, 1 MB, and 8 MB (Chen et al., 2022).

The central performance results are end-to-end. CGTrans reduces SSD loading by approximately $$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$5 on average across datasets, consistent with $$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$6. The complete GRAPHIC system achieves $$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$7 average speedup over GCNAX and $$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$8 average speedup over CGTrans on Insider. On Reddit, the detailed breakdown shows approximately $$Agg = \tilde{D}^{-1/2}\tilde{A}\tilde{D}^{-1/2} H^{(l)}.$$9 latency reduction versus GCNAX, with the principal contributor being the drop in SSD transfer latency (Chen et al., 2022).

The broader gather-and-scatter substrate also shows gains beyond GCN inference. With a 1 MB FAST-GAS and idle-skip, GRAPHIC reports an average $k$0 speedup over a conventional cache for Feature Embedding, BFS, SSSP, and CC, and $k$1 improvement over prior near-SSD solutions. This suggests that the architectural primitive is not limited to message-passing neural workloads but targets a wider class of sparse reduction- and propagation-dominated graph computations.

6. Limitations, scope, and significance

GRAPHIC does not attempt to move all GNN computation into SSD. The MLP remains on the host because dense compute is better served by large PE arrays and DRAM bandwidth. The in-SSD substrate supports sum, min, and max reductions, which makes it suitable for GraphSAGE-style aggregation and several classical graph algorithms, but more complex GNN primitives, such as attention with dynamic per-edge linear transforms, may require additional in-SSD logic or more round-trips (Chen et al., 2022).

The design also assumes nontrivial SSD architectural changes. Integrating CAM plus FAST-SRAM as the SSD cache requires modifications to SSD controller firmware and datapaths. Verification, reliability under power loss, and wear implications for frequent in-place updates remain engineering concerns. Portability across SSD products is likewise conditional: the design is intended to exploit internal SSD parallelism by instantiating GAS per cache or bank, but the exact scaling depends on vendor-specific channel and die organizations that are not standardized in the paper (Chen et al., 2022).

Within those constraints, GRAPHIC establishes a storage-centric formulation of large-scale graph acceleration: aggregation is made to “live where the data lives,” while dense combination remains host-resident. This division is neither a general replacement for accelerator ASICs nor a pure storage optimization. Rather, it is a heterogeneous execution model in which semantic reduction at the SSD boundary converts raw neighborhood traffic into compact per-node aggregates, thereby rebalancing the end-to-end graph pipeline around the actual bottleneck at terabyte scale.