Edge-INC: Programmable In-Network Computing

Updated 3 February 2026

Edge-INC is an in-network computing paradigm that embeds tasks like transcoding, inference, and aggregation directly into programmable edge and node devices, reducing latency and network overhead.
The architecture integrates a data plane of programmable switches, an SDN-controlled control plane, and adapter layers to manage function slices for applications such as XR, federated learning, and distributed ML inference.
Edge-INC advances research by combining systems engineering with combinatorial and algebraic theory to optimize network scheduling, secure aggregation, and overall computational efficiency.

Edge-INC denotes the paradigm of In-Network Computing (INC) with a focus on the structural, algorithmic, and architectural deployment of computation inside the network—particularly programmable edge and node devices. Edge-INC encompasses both applied systems work (packet processing, collective operations, edge-cloud inference, federated learning aggregation) and fundamental mathematics (combinatorial invariants, algebraic edge ideals, extremal polytopes). The following sections survey the main research dimensions and theoretical principles underpinning Edge-INC in current literature.

1. Foundational Definitions and Architectural Principles

Edge-INC refers to embedding computation—aggregation, compression, inference, transcoding—within programmable network elements situated at the network's edge or at host network interfaces. This stands in contrast to classical edge computing, in which tasks are delegated to dedicated servers adjacent to the network fabric. INC as applied at the edge leverages programmable switches (e.g., P4), SmartNICs (sPIN, Portals-4), and host adapters to perform stateless functions at wire speed, directly in the forwarding path without staging to host CPU or DRAM (Gherari et al., 2023).

Key architectural layers:

Data plane: Built from a mesh of P4-programmable switches, or Edge-INC NICs, capable of hosting lightweight computation as externs.
Control plane: An SDN controller orchestrates the mapping and installation of computation modules, including match/action tables and program bindings.
Adapter layer: Abstracts underlying switch heterogeneity, exposing uniform APIs for slice or function management.
Slice embedding layer: Maintains catalogs of compiled INC programs (transcoding, compression, rendering) and provides a resource inventory via real-time telemetry (Aghaaliakbari et al., 2023).

2. Edge-INC in Holographic and XR Applications

Holographic telepresence and multisensory XR pose extreme demands: ultra-low latency (≤5 ms), massive per-stream bandwidth (up to 100 Gbps), and stringent jitter budgets (<15 ms ITU threshold). Standard edge-compute paradigms—routing packets to servers—amplify average end-to-end latency and network load, especially as raw hologram data must traverse multiple hops before reduction (Aghaaliakbari et al., 2023).

INC-enabled slice architectures instantiate computation inside the switch fabric. Upon application request, fields specifying E2E delay, bandwidth, and participant geography constrain slice-embedding algorithms (e.g., virtual network embedding or constrained shortest-path). INC modules—such as stateless transcoders—are mapped to switches via CPU-aware heuristics to minimize added per-hop delay and path traffic volume.

Quantitative results from Mininet-based simulation (11 BMv2 P4 switches, 12 Mbps links):

INC placement increases slice setup overhead by ~60 ms (one-time pre-concert cost).
INC near-source transcoding yields best latency (5–10% reduction vs edge-compute baselines).
Network load is reduced by up to 50% (e.g., $\rho \approx 0.35$ vs $0.9$ for edge-only).
Jitter is well-controlled (5–8 ms for INC; all cases $<$ 15 ms) (Aghaaliakbari et al., 2023).

The same architectural principles suffice—with minor modifications—for ultra-low latency scenarios ranging from VR/AR streaming, remote robotics, IoT sensor fusion, and distributed ML aggregation.

3. In-Network Collective Operations and Communication Offload

Edge-INC, as realized in collective communication for AI workloads, offloads collective primitives to network interface cards (NICs), replacing CPU-driven staging with hardware-triggered packet forwarding and aggregation (Hoefler et al., 27 Jan 2026). Typical Edge-INC NICs store state machines per communicator, perform nonblocking collectives, and overlap accelerator computation with NIC-resident streaming.

Analytical performance model:

Baseline Allreduce (host-DRAM): $T_{\text{comm,baseline}} = \alpha + \beta M + 2\,M/B_\text{mem}$
Edge-INC: $T_{\text{comm,edge}} = \alpha_\text{edge} + \beta_\text{edge} M$
Speedup: $S = \frac{T_{\text{total,baseline}}}{T_{\text{total,edge}}}$

Empirical evidence: 8 GiB Allreduce drops from 352 ms baseline to 151 ms with Edge-INC ( $2.33\times$ comm-phase speedup), yielding overall iteration speedup $\sim13\%$ in large-scale LLM training (Hoefler et al., 27 Jan 2026).

Critical adoption barriers include low-precision data, vector and sparse datatypes, reproducibility requirements (bitwise identical floating-point reduction), endpoint/NIC coordination overhead, and packet-level security (encryption, authentication). Deployment is anticipated first in single-switch scenarios with limited collectives and in standardized Ethernet clusters.

4. Edge-INC for Distributed Inference and Edge-Cloud Collaboration

Edge-INC principles extend to distributed ML inference, where computation splits dynamically between resource-constrained edge models and high-accuracy cloud backends. The ECCENTRIC framework formalizes this via a triply-objective optimization: performance, compute, and communication (Kamani et al., 12 Nov 2025).

Key mechanisms:

Knowledge adaptation modules learn mappings from intermediate edge-layer features to proxy cloud-layer features.
Multi-objective Pareto-descent (Miettinen’s method) weights gradients from each objective to trace the Pareto frontier.
Dynamic inference rules route samples to edge-only, partial-offload (feature map only), or full cloud completion based on edge confidence.

Empirical classification/detection studies (CIFAR-10, COCO, YOLOv5) show ECCENTRIC's dynamic variant matches cloud accuracy while retaining 57% compute and 54% communication. This demonstrates that Edge-INC can flexibly navigate the trade-off space between latency, bandwidth, and accuracy for real-world distributed inference.

5. Algebraic and Combinatorial Theory: Edge-INC Chains and Invariants

Edge-INC has a mathematical interpretation through algebraic invariants of edge ideals and combinatorial optimizations in graph theory.

Inc-Invariant Chains of Edge Ideals

Consider a chain of edge ideals $(I_n)$ invariant under the Inc monoid of strictly increasing maps. Main results (Hoang et al., 2022, Hoa et al., 2024):

Stability: For $n \geq N$ , regularity $\text{reg}(I_n)$ stabilizes to either $2$ or $3$—read off from initial edge set configuration.
Depth: For $n\geq 3r$ (stability index), depth $\text{depth}(R_n/I_n)$ stabilizes to $s$ or $\min(s,2)$ , determined by pivot and sparsity indices of the initial graph. Projective dimension thus obeys a linear regime: $\text{pd}(I_n)=n-\text{depth}(R_n/I_n)$ .
Independence complex homology: Reduced homology groups $\widetilde H_i(\text{IN}(G_n))$ vanish for $i\neq 0,1$ , and are dimensionally governed by combinatorial structure (connectedness, cycles, chordality).
Concrete criteria for regularity $2$ or $3$ rest on non-existence/buildability of long anticycles and induced matchings.

Edge Inducibility and Extremal Polytopes

Edge-INC also encompasses inducibility problems: maximizing induced substructure counts under cardinality constraints (Chao et al., 28 Sep 2025). The edge inducibility $\eind(G)$ for graph $G$ is defined as the normalized limsup over host edge counts. Exact values are determined for all $v(G)\leq 4$ ; bounds for cycles and paths leverage entropy-based and local digraph constructions.

Edge polytopes $P(G)$ —the convex hull of column vectors from the vertex–edge incidence matrix—exhibit extremal facets:

$k$ -neighborly polytopes correspond to forbidden subgraphs and cycle restrictions.
Facet counts scale exponentially: $4^{\lfloor d/3\rfloor} < f(d) \leq 2^d + d$ in dimension $d$ (Tran et al., 2013).
Combinatorial constructions (fundamental/acceptable sets) enumerate supporting hyperplanes.

6. Optimization, Scheduling, and Federated Learning Aggregation

Edge-INC enables decentralized federated learning aggregation at edge nodes, dramatically reducing cloud burden and network latency (Dinh et al., 2021). The architecture comprises:

Mobile users with local datasets.
Edge nodes (ENs) with limited fronthaul/backhaul.
Cloud node with high-capacity uplink/downlink.

Protocols employ bipartition user scheduling to mitigate straggler effects, in-network aggregation (INA) supporting both primal and primal-dual FL variants, and randomized rounding algorithms for joint routing and rate allocation—provably near-optimal and bi-criteria approximating the LP lower bound.

Simulation (up to $K=5000$ users):

$5.6\times$ reduction in FL training latency vs server-only aggregation; cloud uplink traffic and computation drop by factors matching $K/M$ .

7. Challenges, Generalizations, and Open Directions

Edge-INC research identifies several technical and regulatory challenges:

Hardware memory constraints on switches/NICs, energy-aware scheduling, programmable pipeline limitations.
Net neutrality, privacy, and commercial incentive mechanisms for in-fabric compute.
Dynamic code deployment safety, policy audit via blockchain attestations.
Generalization to the "4C" paradigm (adding Control), integration with semantic communication, autonomous network operation.
Mathematical generalizations: stability, inducibility, and extremal geometry of edge-related structures.

Edge-INC architectures have demonstrated fundamental advances in supporting ultra-low-latency, high-bandwidth applications and enabling distributed algebraic and combinatorial optimizations. Research continues to expand the paradigm's formalization, deployment, and integration across networking and computational disciplines.