Dual-System Architecture

• Dual-System Architecture is a design pattern that decomposes computing roles into complementary subsystems to address heterogeneous objectives such as timing determinism and noise isolation.
• It leverages role separation, including exposure-versus-criticality and fast-versus-slow memory distinctions, to optimize performance in applications like IIoT, reinforcement learning, and signal processing.
• Practical implementations demonstrate improvements in security, optimization accuracy, and throughput while highlighting trade-offs like increased system complexity and communication latency constraints.

Searching arXiv for recent and representative papers on dual-system architectures across systems, learning, and signal processing. In the cited literature, the term dual-system architecture is used for designs that split responsibilities across two differentiated subsystems and then re-couple them through a controlled interface. The split may separate network-facing and real-time-critical control in industrial devices, policy optimization and value estimation in reinforcement learning, explicit and implicit subsystems in continual learning, waveform and spectrum processing in speech enhancement, or prediction and verification in medical diagnosis (Niedermaier et al., 2019, Aitchison et al., 2022, Gowda et al., 2023, Zhang et al., 2021, Chen et al., 6 Jun 2026). This suggests that dual-system architecture is best understood as an architectural pattern rather than a single blueprint: one subsystem is typically assigned a role that is exposed, noisy, fast-adapting, feature-rich, or exploratory, while the other is lean, stable, constrained, long-horizon, or verifying.

1. Conceptual scope

A recurring feature of dual-system architecture is role separation. In the secure dual-MCU architecture for IIoT devices, the Network MCU (NW-MCU) handles “all network-facing, non-critical, and potentially attack-exposed functionality,” while the IO MCU (control/IO MCU) handles the “time-critical control loop and direct interaction with sensors/actuators,” and “the physical process must not depend on the timing behavior of the network stack” (Niedermaier et al., 2019). In "DNA: Proximal Policy Optimization with a Dual Network Architecture," the split is between a policy network $\pi_\theta$ and a value network $V_\phi$, motivated by an “order-of-magnitude mismatch in gradient noise” between policy learning and value regression (Aitchison et al., 2022). In DUCA, the explicit–implicit distinction appears as a Working Model / Explicit Module, an Inductive Bias Learner (IBL), and a Semantic Memory (SM); the paper describes this as a dual-representation view combining explicit knowledge with implicit bias and consolidated semantic knowledge (Gowda et al., 2023).

The same pattern recurs in systems that are not obviously cognitive or control-oriented. DBNet uses a dual-branch structure with alternate interconnection, where one branch models the spectrum and the other the waveform, because “Impulse-like noise is easier to remove in the time domain” while “Narrowband noise is easier to suppress in the frequency domain” (Zhang et al., 2021). Duet promotes processors and embedded FPGAs (eFPGAs) to “equal peers” through non-intrusive, bi-directionally cache-coherent integration (Li et al., 2023). The epilepsy diagnosis framework explicitly defines two coordinated components running in parallel: a main discrimination system and a verification system (Chen et al., 6 Jun 2026).

This breadth indicates that dual-system architecture does not denote a specific substrate. It can be realized as two MCUs, two cores, two networks, two branches, two memory systems, or two decision layers. A plausible implication is that the unifying principle is not physical duplication but decomposition by computational function.

2. Recurrent partitioning patterns

One recurrent pattern is exposure-versus-criticality separation. The IIoT dual-MCU design isolates attack-prone communication from safety- and timing-critical IO control, and explicitly frames the design principle as “containment of compromise”: even if the network side is attacked, the control side continues to behave predictably (Niedermaier et al., 2019). SecureD adopts a related but distinct split in a dual-core embedded processor, combining runtime basic-block checksum verification for code-injection attacks with synchronized complementary execution against power analysis attacks; a shared CONTROLLER coordinates both cores, with separate instruction and data memories per core and security-specific registers such as hashedReg and incHashedReg (Ragel et al., 2015).

A second pattern is optimization-statistics separation. DNA argues that standard shared-backbone actor-critic learning is suboptimal because policy gradients are much noisier than value regression. It therefore assigns policy optimization and value learning to separate networks, and then uses a third phase—constrained distillation—to recover useful shared information under a KL constraint (Aitchison et al., 2022). The reported gradient-noise scales, $\sigma_\pi \approx 220.5$ and $\sigma_V \approx 17.5$, differ by about 12.6×, and the tuned return-estimation parameters are deliberately unequal: $\lambda_\pi = 0.8$ and $\lambda_V = 0.95$ (Aitchison et al., 2022).

A third pattern is fast-versus-slow memory separation. DUCA places a fast task-adapting learner in the working model, a shape-based implicit prior in the IBL, and gradual consolidation in semantic memory, explicitly invoking “fast and slow learning systems” and the complementary learning system (Gowda et al., 2023). KairosHope extends this memory-centric form with a HOPE block that replaces quadratic attention by a dual-memory system: Titans modules for “dynamic short-term retention” and a Continuum Memory System (CMS) for “the abstraction of long-term historical context” (Balderas et al., 18 May 2026).

A fourth pattern is complementary representation separation. DBNet uses waveform and Shift Real Spectral views of the same utterance, with a bridge layer to exchange information between them (Zhang et al., 2021). The DFRC hybrid beamforming design introduces an integrated sensing and security (I2S) symbol, whose role is explicitly dual: it acts like artificial noise from the communication viewpoint and contributes useful probing energy from the radar viewpoint (2403.07655). In each case, the dualization is not redundancy but complementarity.

3. Interfaces, synchronization, and information transfer

Dual-system architectures are defined as much by their interfaces as by their subsystem boundaries. In the IIoT design, the MCUs communicate over SPI, with the NW-MCU as the SPI master and the IO MCU as the SPI slave, at a reported speed of 13.5 Mbit/s. The exchange is deliberately polling/timeout-based, not event-driven: the IO-side SPI receive timeout is 500 μs, interrupts and DMA are deliberately not used, and the goal is to bound communication latency while preserving a 1 ms cycle time (Niedermaier et al., 2019). The controlling equation is

$$t_{cycle} = t_{read\_in} + t_{comm} + t_{calc} + t_{write\_out},$$

with compensation

$$t_{delay} = t_{cycle} - (t_{read\_in} + t_{comm} + t_{calc} + t_{write\_out}),$$

so that timing variability is absorbed into $t_{delay}$ rather than propagated into the physical process (Niedermaier et al., 2019).

SecureD uses a different interface logic: a CONTROLLER orchestrates startBal and endBal, routes interrupts, synchronizes PCs, and preserves lock-step execution during complementary encryption. The paper reports a total switching/interruption cost of 748 cycles, broken down as $320 + 30 + 20 + 320 + 30 + 20 + 6 + 1 + 1$ (Ragel et al., 2015). The architectural requirement is cycle-accurate synchronization, because the side-channel countermeasure depends on both cores executing “the same instruction sequence,” “at the same cycle,” with “complementary operands” (Ragel et al., 2015).

In learning systems, the interface is usually an objective rather than a bus. DNA’s constrained distillation phase minimizes

$V_\phi$0

with gradients flowing only through the policy network (Aitchison et al., 2022). DUCA couples its modules through bidirectional knowledge-sharing loss and semantic-memory alignment losses, while the semantic memory is updated stochastically via

$V_\phi$1

with $V_\phi$2 across datasets (Gowda et al., 2023).

DBNet’s interface is a bridge layer: a linear unit converts features from one branch into a form consumable by the other, and the translated features are concatenated with in-branch skip connections inside both encoder-decoder paths (Zhang et al., 2021). Duet’s interface is a coherence substrate: a hardware Proxy Cache participates in the system-wide coherence protocol on behalf of the eFPGA, an optional soft cache sits behind it, and the Proxy Cache “does not require acknowledgements from the soft cache,” which allows the fast clock domain to respond promptly while invalidations are forwarded asynchronously (Li et al., 2023).

At the decision level, the epilepsy framework uses a confidence-consistency rule rather than shared internal states. Its combined score is

$V_\phi$3

with the policy: confidence > 0.92 and agreement gives direct output, $V_\phi$4 and agreement gives output with caution or further verification, and disagreement yields no definitive automatic diagnosis (Chen et al., 6 Jun 2026).

4. Formal objectives and system behavior

Dual-system architectures often become explicit only when their coordination is written as a constrained objective. In IIoT control, the formalism expresses timing isolation: the IO loop remains deterministic if

$V_\phi$5

and the design uses waiting as a feature rather than a bug, since deterministic timing is preserved by intentional slack (Niedermaier et al., 2019). In SecureD, the relevant quantities are overhead and switching cost: the reported area overhead is 3.80%, and the average runtime overhead is 20.0% relative to a standard dual processing system (Ragel et al., 2015).

In DNA, the dualization is formalized through separate return estimators and update schedules. The policy objective remains PPO’s clipped surrogate plus entropy bonus, while the value objective is an independent squared-error loss against a TD($V_\phi$6) target. The core prescription is

$V_\phi$7

reflecting the claim that policy gradients prefer lower variance while value regression prefers lower bias (Aitchison et al., 2022). The practical training loop is correspondingly tripartite: policy optimization, value optimization, and distillation (Aitchison et al., 2022).

In DUCA, the formal structure combines supervised learning on current and replayed data with cross-module knowledge sharing and slow consolidation. Only semantic memory is used at test time, even though training uses three networks, indicating that a “dual” architecture may be defined by explicit-versus-implicit functional decomposition rather than a literal two-module count (Gowda et al., 2023). KairosHope similarly uses a dual-memory core but supplements it with a Hybrid Decision Head that concatenates encoder latent embeddings with deterministic statistical features extracted via the tsfeatures package. Its pretraining objective is

$V_\phi$8

followed by a Linear Probing and Full Fine-Tuning (LP-FT) protocol to prevent catastrophic forgetting (Balderas et al., 18 May 2026).

The DFRC system formulates dual-function operation as a robust optimization problem: maximize the minimum legitimate-user rate subject to radar SINR, eavesdropping rate, hardware, and power constraints (2403.07655). This is an especially clear case in which the “dual” character is neither redundancy nor modular convenience; it is a simultaneous optimization over sensing and secure communication.

5. Representative realizations and reported outcomes

The literature includes hardware, reinforcement learning, continual learning, signal processing, heterogeneous computing, and medical diagnosis instantiations of the dual-system pattern.

Instantiation	Subsystem split	Reported outcome
Secure dual-MCU IIoT (Niedermaier et al., 2019)	NW-MCU / IO MCU	1 ms cycle with about 10 μs jitter; at 10 ms, stable under attack; Wago PLC can increase to 100 ms and about 300% jitter
DNA for PPO (Aitchison et al., 2022)	Policy network / value network + constrained distillation	Atari-5 score 252 for DNA versus 81 for PPO (basic)
SecureD (Ragel et al., 2015)	Dual core with code-injection checks and complementary balancing	3.80% area overhead; 20.0% average runtime overhead
DUCA (Gowda et al., 2023)	Working model / IBL / semantic memory	Seq-CIFAR10 70.04 (buffer 200) and 76.20 (buffer 500); reduced task recency bias
DBNet (Zhang et al., 2021)	Spectrum branch / waveform branch	DNS Challenge overall 3.19 versus 3.07 for NSnet2; top 8 in real-time track 1
Duet (Li et al., 2023)	Processors / eFPGAs as equal peers	Communication latency reduced by up to 82%, bandwidth increased by up to 9.5x, application speedup 1.5-24.9x
KairosHope (Balderas et al., 18 May 2026)	Titans / CMS dual-memory HOPE block	Mean Accuracy 80.11%, Mean F1 0.786
Epilepsy diagnosis (Chen et al., 6 Jun 2026)	Main discrimination system / verification system	Accuracy increased from 92.6% to 98.7%; F1 increased from 0.895 to 0.992; verification feedback integration 220 ms

These results show that the benefits attributed to dual-system architecture are heterogeneous. In control and security systems, the main reported advantage is timing isolation or resistance to attack-induced disruption (Niedermaier et al., 2019, Ragel et al., 2015). In learning systems, the gains are expressed as better optimization statistics, reduced task recency bias, or improved downstream classification (Aitchison et al., 2022, Gowda et al., 2023, Balderas et al., 18 May 2026). In signal processing and heterogeneous hardware, the gains are improved quality or throughput under real-time or coherence constraints (Zhang et al., 2021, Li et al., 2023). In medical AI, the dualization supports both accuracy and clinically oriented verification (Chen et al., 6 Jun 2026).

6. Trade-offs, limitations, and misconceptions

The literature also makes clear that dual-system architecture is not free. The IIoT dual-MCU design requires two MCUs instead of one, “increased system integration complexity,” and communication latency bounds that “must be engineered”; the PoC is robust in timing terms, but “the SPI link itself is not cryptographically secured,” and the paper notes future work such as power separation and galvanic isolation (Niedermaier et al., 2019). SecureD reports low area overhead but a nontrivial runtime increase, showing that hardware/software co-design can shift cost from silicon to execution time (Ragel et al., 2015). DBNet explicitly notes that the dual-branch structure increases computation and therefore uses group LSTM, 64 channels, and a latency budget of 30 ms to remain real-time (Zhang et al., 2021).

In other domains, the cost appears as system complexity rather than raw overhead. DNA requires different minibatch sizes, separate return estimators, separate update epochs, and a distillation phase; the paper’s ablation table shows performance regressions when distillation is removed, when the policy minibatch is reduced, or when $V_\phi$9 (Aitchison et al., 2022). DUCA requires rehearsal, reservoir sampling, knowledge-sharing losses, and stochastic semantic consolidation (Gowda et al., 2023). Duet’s benefits depend critically on the fact that soft accelerators operate at only about 8%–28% of processor frequency, making fast-domain proxying essential; without that architectural choice, FPGA-side participation in coherence would stall the critical path (Li et al., 2023).

Several common misconceptions are corrected by the cited work. First, dual-system architecture is not equivalent to redundancy. The IIoT paper explicitly states that the pattern is “not just about redundancy or fault tolerance” but about “hard separation of cyber-risk from physical actuation timing” (Niedermaier et al., 2019). Second, it is not synonymous with cryptographic security: the dual-MCU PoC relies on architectural isolation rather than cryptographic isolation (Niedermaier et al., 2019). Third, it need not imply exactly two physical modules. DUCA uses three networks during training but remains a dual cognitive architecture because the central distinction is explicit versus implicit knowledge representation (Gowda et al., 2023). Fourth, dualization does not guarantee universal superiority: KairosHope is strongest on HAR and Sensor data but weakest on IMAGE-type one-dimensional contour datasets, which the report attributes to an inductive bias mismatch (Balderas et al., 18 May 2026).

Taken together, these works indicate that dual-system architecture is a reusable design pattern for situations in which one computational regime cannot simultaneously satisfy all requirements. The regime split may target timing determinism, side-channel masking, gradient-noise isolation, lifelong consolidation, cross-domain feature complementarity, cache-coherent acceleration, or explainable verification. What remains constant is the architectural wager that controlled separation plus deliberate recoupling can outperform a monolithic design when the underlying objectives are heterogeneous.