DDMTD Phase Detection for Pulsed Lasers

• DDMTD Phase Detection is a technique that combines analog error amplification with FPGA-based digital phase demodulation to achieve sub-femtosecond resolution in pulsed laser stabilization.
• It uses dual ADC sampling and digital quadrature mixing to cancel common-mode jitter and enable high-fidelity phase tracking via a digital PID feedback loop.
• The method leverages frequency down-conversion and error amplification to deliver near–atomic-clock-level stability, making it ideal for precision optical metrology.

The digital dual-mixer time-difference (DDMTD) phase-detection technique offers a compact, high-precision approach for measuring and stabilizing the repetition frequency of pulsed lasers. By integrating a front-end phase and timing error amplifier with a fully digital, FPGA-based time-difference measurement algorithm, the system achieves phase-detection resolution and long-term frequency stability approaching that of atomic clocks—without requiring ultra-high-speed analog hardware or specialized analog time-interval counters. This architecture fundamentally relies on a dual-path strategy: analog frequency error amplification and down-conversion to a manageable intermediate frequency, followed by digital phase discrimination using high-resolution, moderate-speed ADCs (Zheng et al., 2024).

1. System Architecture and Components

The DDMTD phase-detection system comprises two principal subsystems: the Error Amplification Module (EAM) and the Digital Frequency Locking Module (DFLM). The EAM consists of a photodiode receiver, a band-pass filter isolating the laser’s fundamental repetition frequency ($f_x = f_0 + \Delta f$), a configurable frequency multiplier (CFM) implemented as a PLL with integer multiplication factor $m$, and a configurable frequency generator (CFG) that produces a clean mixing tone ($f_m = m f_0 - f_r$) referenced to a high-stability atomic clock ($f_r$). Mixing $m f_x$ and $f_m$ yields an error tone ($f_e = f_r + m \Delta f$), which down-converts the error and amplifies it by $m$.

In the DFLM, two synchronized ADCs digitize the EAM output ($f_e$) and the atomic reference. Both are digitally mixed with an on-FPGA numerically controlled oscillator (NCO) at $f_{\text{nco}} \approx f_r$, producing quadrature baseband components. Subsequent digital low-pass filtering, arctangent-based phase extraction, and differential phase computation remove common jitter, enabling high-fidelity phase tracking. A phase-unwrapped error signal is differentiated and processed via a digital PID filter, ultimately actuating a piezoelectric transducer (PZT) for laser cavity length stabilization.

2. Error Amplification and Frequency Down-Conversion

Core to the DDMTD approach is the analog amplification and translation of phase and timing errors from the laser’s repetition train through frequency multiplication and mixing. With $m$0, the multiplier output is $m$1, and the mixing tone is $m$2. The mixer’s low-pass output becomes $m$3. Timing errors $m$4 in the laser’s pulse train yield phase errors $m$5, which are amplified by $m$6 through the frequency translation process, such that the equivalent output timing error is $m$7. This process boosts sensitivity and shifts the signal to a frequency range suitable for ADC-based measurement.

3. Digital ADC-Based Dual-Mixer Algorithm

Within the DFLM, the ADC-based DDMTD algorithm operates as follows:

1. Synchronous Sampling: Dual 16-bit ADCs sample both $m$8 and the reference $m$9 at $f_m = m f_0 - f_r$0 MS/s.
2. Digital Quadrature Mixing: Each signal is digitally mixed with sine and cosine NCO outputs, generating $f_m = m f_0 - f_r$1 and $f_m = m f_0 - f_r$2, then low-pass filtered.
3. Phase Extraction: Phases $f_m = m f_0 - f_r$3 and $f_m = m f_0 - f_r$4 are calculated.
4. Jitter Cancellation and Differencing: The phase difference $f_m = m f_0 - f_r$5 cancels common-mode NCO and sampling jitter.
5. Phase Unwrapping: Discontinuities are tracked to produce an unwrapped sequence $f_m = m f_0 - f_r$6 via hardware counters.
6. Frequency Estimation: Instantaneous frequency is estimated as $f_m = m f_0 - f_r$7 or, for long-term averaging, with windowed differences.
7. Feedback Filtering and Output: The error signal is filtered by a digital PID and converted to an analog correction.

The quantization-limited timing resolution is $f_m = m f_0 - f_r$8, enabling sub-femtosecond discrimination with sufficient SNR (14–16 bits) and integration time (Zheng et al., 2024).

4. Measurement Performance and Experimental Results

Performance is benchmarked at both the phase measurement and feedback stabilization stages. In two-channel split tests, the system achieves an Allan deviation $f_m = m f_0 - f_r$9, improving by nearly an order of magnitude over traditional digital quadrature demodulation ($f_r$0) and closely matching commercial phase analyzers ($f_r$1).

In VCO frequency locking, the system reduces the Allan deviation from $f_r$2 pre-lock to $f_r$3 post-lock ($f_r$4), with an RMS frequency STD of $f_r$5 μHz over 8000 s. With a custom femtosecond fiber laser ($f_r$6 MHz, $f_r$7, $f_r$8 MHz), long-term stability improved from $f_r$9 pre-lock to $m f_x$0 after stabilization, for an RMS STD of 0.43 mHz (Zheng et al., 2024).

Experiment	Pre-Lock Stability	Post-Lock Stability	Improvement Factor
VCO	$m f_x$1	$m f_x$2	Five orders of magnitude
Femtosecond Laser ($m f_x$3 MHz)	$m f_x$4	$m f_x$5	Five orders of magnitude

5. Implementation Constraints and Design Trade-Offs

Key implementation requirements include ADCs with sampling rates sufficient for the beat frequency ($m f_x$6 MS/s for $m f_x$7 MHz signals) and at least 14–16 bits of resolution to obtain SNR for sub-femtosecond timing discrimination. FPGA resources must accommodate four real-time multipliers (two channels × I/Q), block RAM for FIFO storage, arithmetic logic for phase computation (e.g., CORDIC engines), and PID filtering.

Trade-offs are present in choosing the error amplification factor ($m f_x$8): increasing $m f_x$9 enhances sensitivity but necessitates higher-frequency PLLs in the front end. Longer digital averaging ($f_m$0) improves phase/frequency resolution but reduces the control loop bandwidth. ADC sampling rates and FPGA clock domain complexity are jointly constrained: higher $f_m$1 drives digital signal processing demand, especially for quadrature demodulation paths (Zheng et al., 2024).

6. Functional Significance and Comparative Advantages

The DDMTD approach, by performing both error amplification in the analog domain and phase/frequency extraction in the digital domain, removes sources of analog zero-crossing noise, cancels common-mode NCO jitter, and averages down high-frequency phase fluctuations. This results in frequency-locking performance previously achievable only using more complex, bulky, or expensive hardware such as ultra-fast ADCs or analog time-interval counters. The system architecture provides flexible, reconfigurable operation suitable for a range of pulse laser sources and repetition frequencies, with demonstrated near–atomic-clock-level frequency stability (Zheng et al., 2024).

A plausible implication is that such architectures will be increasingly favored in precision optical metrology and high-end scientific instrumentation where compactness, reconfigurability, and cost-efficiency are prioritized without sacrificing long-term phase and frequency stability.