Delayed Leakage Reduction (DLR) in QEC and Control
- DLR is a family of delay-based techniques that reassign leakage suppression from the moment of occurrence to a later, less disruptive moment, applicable in QEC, pulse engineering, and discrete systems.
- In quantum error correction, scheduling leakage reduction units later (as in Partial-LRU and Quick) reduces overhead and can enhance logical error performance compared to immediate correction.
- In hardware implementations and pulse shaping, DLR uses timed, delayed replicas of control signals to create spectral notches that curb leakage, offering high-fidelity control without complex modulation.
Searching arXiv for recent and foundational papers on Delayed Leakage Reduction and related leakage-reduction units in QEC. Delayed Leakage Reduction (DLR) is a context-dependent term used for several delay-based strategies that reduce leakage without acting at the instant it is created. In quantum error correction, DLR denotes scheduling leakage reduction units (LRUs) later within or across syndrome-extraction cycles rather than immediately after every leakage event, in order to avoid disrupting concurrent operations and to limit overhead. In pulse engineering, DLR denotes a baseband pulse-shaping method that uses time-delayed replicas of a control signal to suppress leakage at targeted frequencies. In discrete-time updating systems, the same delay principle appears as deliberate postponement of packet release to reduce maximal leakage at the cost of higher age of information (Suchara et al., 2014, Chen et al., 2024, Polat et al., 4 Aug 2025, Sathyavageeswaran et al., 2022).
1. Scope and terminological range
The term is not univocal across the literature. In the surface-code and transmon-QEC literature, DLR is a scheduling concept: leakage is removed in designated windows, typically once per cycle or every cycles, instead of after every gate. In ultra-fast gate design, DLR is a pulse-construction method: delayed replicas of an envelope create spectral notches at known leakage frequencies. In discrete-time privacy-leakage studies, the same acronym can be mapped to delayed release policies that intentionally reduce the information revealed by the output process (Suchara et al., 2014, Polat et al., 4 Aug 2025, Sathyavageeswaran et al., 2022).
| Domain | Operational meaning of DLR | Representative papers |
|---|---|---|
| Topological QEC and surface codes | LRUs scheduled later than “after every gate” | (Suchara et al., 2014, Chen et al., 2024) |
| Superconducting transmon control | Scheduled, unconditional, or batched LRUs using existing hardware primitives | (Battistel et al., 2021, Marques et al., 2023, Lacroix et al., 2023, Camps et al., 2024) |
| Baseband pulse shaping | Time-delayed replicas of a control pulse to notch leakage frequencies | (Polat et al., 4 Aug 2025) |
| Privacy in updating systems | Delayed packet release to reduce maximal leakage | (Sathyavageeswaran et al., 2022) |
A plausible commonality is that DLR reallocates leakage-control effort from the moment of leakage creation to a later point where the control action is cheaper, less disruptive, or more selective.
2. Foundational leakage-reduction operators in fault-tolerant quantum computation
In leakage-resilient fault tolerance, the central primitive is the LRU: an operation that acts as the identity on contained inputs and maps leaked inputs back into the computational subspace. In the toric-code study of leakage suppression, each physical qubit is modeled as a qutrit with Hilbert space , where is the 2-D computational subspace and is the 1-D leakage subspace spanned by . Leakage excitation and relaxation are described by the stochastic maps
and
with decay replacing a leaked qubit by a maximally mixed contained qubit. In that model, interaction with a leaked qubit effectively induces complete depolarization on the contained partner during a two-qubit sealed gate, which makes leakage qualitatively more damaging than standard Pauli noise (Suchara et al., 2014).
Earlier exchange-only work in the 3-qubit decoherence-free subsystem supplied an explicit leakage-reduction operator in a different architectural setting. There, a leaked subsystem corresponds to the sector, while the unleaked computational subsystem is the sector. The exact exchange-only DFS leakage-reduction sequence requires 30 pulses in 20 time steps, and was presented as the first explicit leakage reduction sequence of its kind. In that construction, the leakage-reduction operator returns a leaked DFS qubit to the unleaked manifold while preserving the logical information when the qubit is not leaked, thereby providing a concrete LRU primitive that can be scheduled in a delayed manner (Fong et al., 2011).
These foundations establish the logical structure later used by DLR: leakage need not be removed inline with every entangling operation if a later operation can restore the state to the computational sector before leakage-induced correlations become dominant.
3. Delayed schedules and leakage-aware decoding in topological codes
The clearest formalization of DLR as a scheduling policy appears in leakage suppression for the toric code. That work distinguishes four schedules: No LRU, Full-LRU, Partial-LRU, and Quick. “LRU after every gate” corresponds to Full-LRU. “Delayed LRU” corresponds to Partial-LRU, which applies one LRU per data qubit per cycle after ancilla measurement, and to Quick, which uses periodic swap-and-reset so that each physical qubit is measured and reset every other cycle without an explicit LRU (Suchara et al., 2014).
The overhead differences are substantial. Full-LRU uses 16 extra gates per data and per ancilla qubit per cycle. Partial-LRU uses 4 extra gates per data qubit per cycle and no ancilla overhead. Quick uses one extra CNOT per data qubit per cycle, requires no extra ancillas on the torus, and on planar or rotated codes requires extra boundary qubits for alternating swaps. These schedules were evaluated with Minimum-Weight Perfect Matching on a 3D decoding graph, and, in the heralded-leakage setting, with a conditional decoding graph 0 whose weights are updated according to
1
with heuristic per-interaction edge probabilities
2
and update rule
3
The HL decoder also sets the vertical 4-edges to weight 0 during a contiguous run of “L” outcomes, thereby explicitly incorporating leakage flags into the matching problem (Suchara et al., 2014).
Quantitatively, the threshold trade-off is schedule-dependent. At 5, the thresholds are approximately 6 for No LRU, 7 for Quick, 8 for Partial-LRU, and 9 for Full-LRU. With leakage comparable to depolarizing noise, simple delayed schedules remain competitive: at 0, the fitted form
1
gives approximately 2 for Quick with Standard decoding, 3 for Partial-LRU with Standard decoding, 4 for Quick with HL decoding, and 5 for Partial-LRU with HL decoding. The key crossover is subthreshold: although Full-LRU has the lowest threshold and the largest overhead, its empirical logical-error scaling 6 has 7, compared with 8–9 for Quick and Partial-LRU. Accordingly, when the physical error rate is less than 0, placing LRUs after every gate may achieve the lowest logical error rates among the circuits considered (Suchara et al., 2014).
DLR in this sense is therefore not synonymous with “weaker protection.” It is a scheduling compromise whose desirability depends on the regime: near threshold and with realistic leakage rates, delayed schedules can outperform Full-LRU because the extra locations introduced by aggressive leakage control lower the threshold more than they help.
4. Superconducting-transmon realizations in surface-code-compatible architectures
Transmon-based work has turned DLR from an abstract schedule into a family of concrete hardware primitives. A hardware-efficient surface-code proposal introduced two LRUs without hardware or QEC-cycle-time overhead: a readout-resonator LRU for data qubits, driven by a microwave tone that transfers 1 population to the readout resonator, and an ancilla LRU consisting of a conditional 2 3 pulse triggered by detecting ancilla leakage in dispersive readout. In density-matrix simulations of the distance-3 rotated surface code, the average leakage lifetime was reduced from 4 cycles to 5 cycle, and the logical error rate was reduced by up to 6 for representative parameters 7, 8, 9, and 0 (Battistel et al., 2021).
All-microwave LRUs later demonstrated direct experimental integration into repeated parity measurements. In circuit QED, the 1-LRU drives 2, and the 3-LRU drives 4, using the readout resonator and Purcell filter as a dissipative sink. The pulse envelope uses 5 rise and fall with 6, the total LRU duration is 7, the measured Z-rotation rate is 8, and with virtual-Z correction the average fidelity of the LRU window is 9, compared with 0 for idling over the same 1. In a 50-round weight-2 parity measurement, error-detection probability increased by 2 without LRUs but was limited to 3 with LRUs, while steady-state leakage was reduced from 4 to 5 for all three transmons (Marques et al., 2023).
A flux-activated universal LRU provided a shorter realization. Using parametric flux modulation at the upper sweet spot, the operation resonantly couples 6 to 7, after which the resonator photon decays to the environment. The sideband resonance condition is
8
with effective resonant coupling
9
Experimentally, this LRU removes leakage down to 0 in approximately 1, introduces a computational-subspace error of 2, reduces auxiliary leakage after 50 cycles from 3 to 4, and shortens auxiliary leakage lifetime from 5 cycles to 6 cycle (Lacroix et al., 2023).
A further step is the fixed-frequency transmon protocol with pair-wise tunable couplers. Its model Hamiltonian in the rotating-wave approximation is
7
Here the tunable coupler transfers unwanted qubit excitation into the readout resonator, from which it decays into the feedline. The demonstrated sequence includes a 9 ns adiabatic qubit reset of 8 with 9, a 5 ns coupler-assisted 0 LRU with 1, and a 22 ns coupler–resonator reset with error below 2. When ancilla 3 and 4 reset, data-qubit leakage reduction, and coupler reset are combined and parallelized, the total wall-clock time is 83 ns (Chen et al., 2024).
Collectively, these works show that DLR in transmon devices can be realized as a scheduled window populated by unconditional, measurement-free, or measurement-conditioned LRUs whose durations range from 5 to 6, and whose leakage lifetimes are typically driven toward one cycle.
5. Mobility-based and implicit DLR
DLR need not be implemented only through explicit LRU pulses. In surface-code stability experiments with superconducting qutrit models, leakage mobility itself can act as a leakage reduction unit. In that model, leakage is created during CZ by exchange between 7 and 8 with parameter 9,
0
and leaked excitations can move between qubits through the mobility process
1
2
with 3. Because ancillas are measured and reset every round, leakage that migrates onto ancillas is automatically purged at round end. Under this mechanism, the standard, non-wiggled circuit improves monotonically with increasing leakage mobility, while “patch wiggling,” which alternates data and ancilla roles to ensure explicit reset, becomes inefficient as mobility increases. The reported crossover is around 4 for both 5 and 6 (Camps et al., 2024).
This result alters the usual interpretation of DLR. Instead of scheduling a separate LRU, one can sometimes omit it and rely on ordinary ancilla resets plus mobility-mediated transport. In the terminology aligned by that work, this is still DLR: leakage is not removed where it is created, but is allowed to move until a routine reset removes it. A similar architectural logic appears in the fast tunable-coupler reset protocol, which explicitly notes two scheduling modes: immediate insertion after ancilla readout and before the next stabilizer round, or a DLR-style schedule in which LRUs are batched every 7 cycles or triggered only on qubits suspected of leakage based on anomalous syndromes. Because the operations are unconditional and localized, delayed use does not depend on high-fidelity leakage detection and keeps classical feedback out of the critical timing loop (Chen et al., 2024).
A plausible implication is that “DLR” spans a continuum from explicit delayed LRUs to implicit delayed cleanup by circuit physics, provided the leakage-removal sink—typically ancilla measurement and reset—remains available at high cadence.
6. Pulse-shaping DLR for ultra-fast adiabatic gates
A distinct and explicit use of the term appears in ultra-fast adiabatic gate design. Here DLR is not a scheduling policy but a pulse-shaping method that suppresses leakage for baseband control by using time-delayed repetitions of the control signal. If 8 is a base envelope, the DLR-composed pulse is
9
with frequency-domain transfer factor
0
Leakage suppression at targeted transition frequencies 1 is obtained by imposing
2
For the single-target, two-tap case with 3,
4
so the notch condition is 5, or 6 (Polat et al., 4 Aug 2025).
The application developed in that work is an adiabatic CZ gate between two spin qubits with resonance-frequency difference 7. The exchange Hamiltonian mixes the single-excitation subspace 8, and for 9 the nonadiabatic leakage error is approximated by
00
where
01
DLR-static chooses a fixed delay 02, DLR-average places the notch at the average of the instantaneous oscillation frequencies, and DLR-dynamic uses a time-dependent delay 03 to track the instantaneous 04. In the reported spin-qubit CZ, DLR-dynamic achieves fidelities exceeding 05 within 06 for a resonance frequency difference of only 07 (Polat et al., 4 Aug 2025).
This use of DLR is conceptually different from QEC scheduling, but it preserves the same structural idea: leakage is not countered by an auxiliary correction stage after the fact, but by deliberately delayed replicas that reshape the control spectrum so the leakage channel is never resonantly driven. The contrast with DRAG is explicit. DRAG requires complex IQ modulation and can be unsuitable for baseband-only, strictly positive controls, whereas DLR constructs the spectral notch entirely in baseband. The same work also gives a hardware-sampling criterion,
08
to avoid aliasing-induced loss of the notch (Polat et al., 4 Aug 2025).
7. Delayed release and privacy leakage in discrete-time updating systems
In a non-quantum but formally related setting, delayed release serves as a leakage-reduction mechanism for time-stamped updates. A Bernoulli source with per-slot generation probability 09 feeds a server whose output process is observed by an adversary. The relevant privacy metric is maximal leakage
10
and the question is how server-side delay policies trade leakage against age of information (AoI) (Sathyavageeswaran et al., 2022).
Three policies are analyzed. In Memoryless with Bernoulli Thinning (MBT), each arrival is admitted with probability 11, and the head-of-line update is released with probability 12. In Random Accumulate-and-Dump (RAD), the freshest update is released after a geometric waiting time with parameter 13. In Deterministic Accumulate-and-Dump (DAD), the freshest update is released every fixed 14 slots. For MBT and RAD, the per-slot maximal leakage rate is
15
while for DAD it is
16
The corresponding AoI expressions are
17
18
and
19
For the same maximal leakage rate, DAD achieves lower age than MBT and RAD, but only at discrete operating points because 20 must be an integer (Sathyavageeswaran et al., 2022).
This literature uses “leakage” in an information-theoretic sense rather than a Hilbert-space sense. Even so, the delay principle is directly analogous: fewer or more regular release opportunities reduce the information exposed to an observer, just as deferred or strategically placed LRUs can reduce operational overhead while containing leakage damage in QEC.
Across these literatures, DLR is best understood not as a single protocol but as a family of delay-based leakage-management strategies. In quantum error correction, it organizes when LRUs are applied; in superconducting hardware, it specifies where fast dissipative or microwave primitives are inserted; in adiabatic control, it shapes spectra by delayed replicas; and in update systems, it reduces adversarial inference by delayed release. A plausible synthesis is that DLR becomes attractive whenever immediate leakage suppression is possible but operationally suboptimal.