CSR to AR-CSR Conversion Algorithm

• The paper presents a conversion algorithm that transforms standard CSR into adaptive AR-CSR formats, detailing both GPU-adaptive and CSE-based variants for optimized performance.
• It explains adaptive row grouping with greedy thread assignment, offset computation, and padding strategies to achieve efficient, coalesced memory access on GPUs.
• The article also demonstrates how common subexpression elimination in the CSE-based AR-CSR reduces duplicate arithmetic operations in constant sparse matrices.

A conversion algorithm from Compressed Sparse Row (CSR) to Adaptive Row-grouped CSR (AR-CSR) transforms sparse matrix storage to optimize parallelism, memory access, and arithmetic intensity for architectures such as GPUs. AR-CSR is not a single format, but a designation for blocked or grouped CSR variants that leverage thread-level parallelism or computational reuse through common subexpressions. This article surveys and details both major forms of AR-CSR: (1) Adaptive Row-grouped CSR for GPU execution (Heller et al., 2012), and (2) Adder-Rod CSR exploiting common subexpression elimination for constant matrices (Bilgili et al., 2023), contextualizing them within a formal format-conversion paradigm (Chou et al., 2020).

1. Prerequisites and Standard CSR Format

CSR encodes a sparse $m\times n$ matrix $A$ as three arrays:

• values $[0\,..\,\mathrm{nnz}-1]$: nonzero entries, row-major,
• colIdx $[0\,..\,\mathrm{nnz}-1]$: column indices for each value,
• rowPtr $[0\,..\,m]$: $\mathrm{rowPtr}[i]$ marks the start of row $i$ in values/colIdx.

Given $i$, entries for row $i$ are indexed as $k\in[\mathrm{rowPtr}[i],\,\mathrm{rowPtr}[i+1])$.

AR-CSR formats generalize CSR by focusing on adaptive grouping or arithmetic compression:

• GPU-Adaptive AR-CSR (Heller et al., 2012): Rows are grouped into blocks, with each block mapped to a CUDA-thread block. Thread assignments and data layout are chosen to maximize workload balance and enable coalesced memory access.
• Adder-Rod (CSE-Based) AR-CSR (Bilgili et al., 2023): For pruned/quantized constant matrices, common subexpressions (CSEs) among columns are extracted and encoded to minimize redundant computation and storage.

2. GPU-Adaptive Row-grouped CSR: Algorithms and Data Structures

The canonical AR-CSR for GPU computation (Heller et al., 2012) groups consecutive rows into "row-groups," designed to match CUDA thread blocks. The conversion comprises four phases:

2.1. Row-group Partitioning and GroupInfo Construction

Given tunable parameters blockSize (threads per group/block) and desiredChunkSize (controls regularity vs. padding), rows are assigned into groups subject to:

• Maximum $A$0 rows per group,
• Cumulative nonzeros per group $A$1.

Each group $A$2 is characterized by:

• $A$3: index of first row,
• $A$4: count of rows,
• $A$5: maximum workload (nonzeros handled per thread in $A$6),
• $A$7: start index in packed arrays (computed later).

2.2. Adaptive Thread Assignment (Greedy Splitting)

For each group, assign threads to rows:

1. Initialize each row with 1 thread: $A$8 for $A$9.
2. Allocate remaining threads to the row currently having the largest "chunk" $[0\,..\,\mathrm{nnz}-1]$0, incrementing $[0\,..\,\mathrm{nnz}-1]$1.
3. The final $[0\,..\,\mathrm{nnz}-1]$2.
4. Record mapping in threadMap.

This process balances load across threads within each group:

$[0\,..\,\mathrm{nnz}-1]$3

2.3. Offset Calculation

Compute offsets for packed storage:

$[0\,..\,\mathrm{nnz}-1]$4

2.4. Assembly of AR-CSR Arrays

Allocate storage:

• $[0\,..\,\mathrm{nnz}-1]$5.
• Arrays: $[0\,..\,\mathrm{nnz}-1]$6, $[0\,..\,\mathrm{nnz}-1]$7.

For each group $[0\,..\,\mathrm{nnz}-1]$8 and thread $[0\,..\,\mathrm{nnz}-1]$9, determine which row/chunk to process using exclusive prefix sums and allocate each thread a contiguous, column-major chunk for coalesced memory access.

Padding is inserted as necessary (with $[0\,..\,\mathrm{nnz}-1]$0) to maintain block alignment, enabling early kernel exits.

2.5. Pseudocode Summary

$i$2

2.6. Computational Complexity

• Partitioning: $[0\,..\,\mathrm{nnz}-1]$1.
• Thread assignment: $[0\,..\,\mathrm{nnz}-1]$2.
• Packing: touch every nonzero $[0\,..\,\mathrm{nnz}-1]$3; overall $[0\,..\,\mathrm{nnz}-1]$4 for practical block sizes.

3. Adder-Rod CSR via Common Subexpression Extraction

Adder-Rod (CSE-based) AR-CSR is designed for sparse constant matrices where weight reuse is possible (Bilgili et al., 2023). The conversion pipeline:

3.1 Construction of Per-Column Unique Weights

For each column $[0\,..\,\mathrm{nnz}-1]$5, collect unique weights $[0\,..\,\mathrm{nnz}-1]$6, store in a flat array $[0\,..\,\mathrm{nnz}-1]$7, and record segment boundaries in $[0\,..\,\mathrm{nnz}-1]$8. Each T$[0\,..\,\mathrm{nnz}-1]$9 is mapped to a "weight pointer" $[0\,..\,m]$0.

3.2 Extraction of Two-term CSEs

• Randomly pair columns and, for each pair, identify the most frequent $[0\,..\,m]$1 across all rows.
• Apply a random search (randomly swap columns between pairs) to maximize total gain (number of redundant additions eliminated).
• For each extracted pair with $[0\,..\,m]$2 occurrences, record $[0\,..\,m]$3 and the list of row indices in compressed CSE arrays.

3.3 Assembly of Final Structures

• The remaining unmapped nonzeros are encoded as "singles" per row, in $[0\,..\,m]$4 and $[0\,..\,m]$5.
• Storage:
  • $[0\,..\,m]$6: compressed representation of unique weights.
  • $[0\,..\,m]$7: CSE blocks with pointers and their row indices.
  • $[0\,..\,m]$8: singles per row.

3.4 Complexity

• Weight collection: $[0\,..\,m]$9.
• CSE extraction: $\mathrm{rowPtr}[i]$0 per random search iteration.

3.5 Worked Example

Given a $\mathrm{rowPtr}[i]$1 matrix with all positions nonzero, CSE-based AR-CSR can reduce addition and multiplication count (and array size) versus CSR, as detailed explicitly in [(Bilgili et al., 2023), Section 3].

4. General Format-Conversion Paradigms and Optimization

Formal frameworks such as Chou et al. (Chou et al., 2020) unify a spectrum of blocked and adaptive compressed formats. Conversion routines operate in three structured phases:

• Coordinate Remapping: For each nonzero at $\mathrm{rowPtr}[i]$2, compute its AR-CSR destination indices, e.g., $\mathrm{rowPtr}[i]$3.
• Attribute Analysis: Compute histogram queries to allocate group/row pointers.
• Assembly (Scatter): One or two passes over nonzeros, possibly fusing remapping and positional assignment for efficiency.

This approach supports both hardware-optimized (GPU) and software-oriented (CSE) AR-CSR formats, producing efficient conversion code that avoids explicit temporaries and can be parallelized or vectorized (Chou et al., 2020).

5. Data Layout, Thread Assignment, and Memory Behavior

For the GPU AR-CSR (Heller et al., 2012):

• Each group maps directly to a CUDA thread block; threads are adaptively subdivided among rows to minimize maximum per-thread workload ($\mathrm{rowPtr}[i]$4).
• Storage layout is column-major over threads, ensuring that simultaneous thread accesses map to consecutive physical addresses—this yields fully coalesced memory transactions for both loads and stores.
• Padding with artificial zeros (signaled by $\mathrm{rowPtr}[i]$5) enforces uniform chunk sizes.

For Adder-Rod AR-CSR (Bilgili et al., 2023):

• The layout exploits weight sharing and avoids storing duplicate weights by mapping matrix entries to their unique per-column weights.
• CSE blocks and singles structure the data for efficient traversal and minimal redundancy.

6. Preprocessing Constraints and Parameter Tuning

Key preprocessing requirements and constraints:

• CSR input must have sorted $\mathrm{rowPtr}[i]$6 and valid format.
• No reordering/sorting of column indices; per-row structure is preserved.
• GPU AR-CSR: $\mathrm{rowPtr}[i]$7, with larger values beneficial for uniform matrices, but increasing padding in irregular cases.
• CSE-based AR-CSR: Efficacy depends on nonzero value repetition ($\mathrm{rowPtr}[i]$8 small), and on the structure yielding frequent CSEs across columns.
• General parallelization possible in all phases; e.g., per-thread histograms in analysis phase can avoid atomics when fusing into per-thread buffers (Chou et al., 2020, Heller et al., 2012).

7. Illustrative Example and Practical Considerations

For a $\mathrm{rowPtr}[i]$9 matrix:

• Standard CSR arrays ($i$0) are partitioned into three groups due to chunking rules.
• Each group is handled by a thread block, each row is greedily split onto as many threads as possible (subject to group/block constraints), and chunked for column-major packing.
• Data arrays are padded as required, group descriptors maintained, and thread mapping finalized. The result is a memory layout and thread assignment enabling maximal throughput and efficient block-wise reduction, especially in GPU SpMV kernels (Heller et al., 2012).

For CSE AR-CSR, given a $i$1 matrix with repetitive values, the construction yields compressed arrays with minimal redundant additions, as detailed stepwise in (Bilgili et al., 2023), demonstrating storage and runtime savings versus CSR in settings where constant (pruned, quantized) matrices are typical.

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In summary, conversion from CSR to AR-CSR is a structured, multi-phase process that enables adaptive, hardware-aware, and application-driven storage reorganization. The concrete algorithmic steps and data layouts depend on the targeted variant—whether for maximizing SIMD/thread efficiency or for exploiting arithmetic redundancy. The pattern illustrated in the cited works provides a rigorous pipeline for high-performance sparse matrix storage and computation (Heller et al., 2012, Bilgili et al., 2023, Chou et al., 2020).