CNOT Gate-Scheduling for Stabilizer Measurement

• The paper demonstrates that a five-slot, hook-error-avoiding CNOT schedule improves logical error rates and, at low noise rates, outperforms standalone patch arrangements.
• The methodology employs a 2×2 checkerboard tiling of four scheduling patterns (A–D) to avoid simultaneous qubit contention and enforce stabilizer precedence.
• Monte Carlo simulations and pseudocode confirm that the approach reduces physical qubit overhead by ~25% while maintaining error-correcting capabilities in dense surface code layouts.

CNOT gate-scheduling for stabilizer measurement in the context of densely packed surface codes addresses the design of time-ordered two-qubit (CNOT) gate operations during syndrome extraction, with explicit emphasis on suppressing the propagation of hook errors. The resulting schedules are essential for maximizing the logical distance, preserving error-correcting capabilities, and enabling practical space savings in multi-codeword architectures.

1. Qubit Layout in the Densely Packed Surface Code

The rotated (45°) surface code in densely packed form organizes data qubits and stabilizer ancillas on a two-dimensional checkerboard. Data qubits (“*”) are situated at lattice vertices, Z-type ancillas (“Z”) and X-type ancillas (“X”) sit at face centers, and unused or “hallway” sites (“.”) are interleaved. In a “row” of five linearly fused code patches—serving as the minimal nontrivial example—the layout in $(y,x)$ coordinates is:

.	Z	.	Z	.	Z	.	Z	.
Z	*	Z	*	Z	*	Z	*	Z
.	X	.	X	.	X	.	X	.
X	*	X	*	X	*	X	*	X
.	Z	.	Z	.	Z	.	Z	.
Z	*	Z	*	Z	*	Z	*	Z

Each stabilizer ancilla interacts with four neighboring data qubits (degree-4). Along “seams” between patches, faces preserve weight-4 connectivity while their supports straddle multiple codewords. Logical qubits are located at the centers of the central ancillas in the middle band.

2. Fundamental Scheduling and Hook-Error Constraints

Syndrome extraction proceeds through the following stages: (i) ancilla preparation ($|0\rangle$ or $|+\rangle$), (ii) execution of $T$ CNOT time slots, (iii) ancilla measurement, (iv) classical decoding.

Two fundamental constraints define valid CNOT gate schedules:

• Constraint 1 (No simultaneous contention): Each data qubit and each ancilla may participate in at most one CNOT per time slot.
• Constraint 2 (Stabilizer precedence): For neighboring stabilizer ancillas sharing two data qubits, both CNOTs from one must precede both from the other. Formally, if $X_1, X_2$ are the assigned CNOT times for stabilizer $A$ and $Z_1, Z_2$ for neighboring stabilizer $B$, then either $X_1 < X_2 < Z_1 < Z_2$ or $Z_1 < Z_2 < X_1 < X_2$.
• Hook-error-avoiding scheduling:
  • Lemma (Hook-error direction): In the standard weight-4 circuit, a single Pauli error on an ancilla between its $k$-th and $(k+1)$-th CNOT propagates to a two-qubit Pauli on those data lines. If those data lines lie along the logical operator direction, logical distance is compromised.
  • The schedule must ensure for each ancilla that the last two CNOTs in its sequence span a chord orthogonal to the logical operator of the encoded logical qubit. This suppresses reductions in code distance resulting from ancilla faults.

These constraints are necessary for ensuring both locality, conflict-free parallelism, and preservation of logical distance in syndrome extraction rounds.

3. Five-Step CNOT Scheduling Patterns

Due to adjacency sharing in dense code layouts, a five-step ($T=5$) CNOT schedule is required—an increase of one time slot compared to the standalone (unfused) surface code. Each ancilla is assigned one of four local “patterns” (A, B, C, D), determining the ordering of its four neighbor CNOTs over the five available time slots. The mappings are:

Pattern	N	E	S	W
A	1	2	3	4
B	4	1	2	3
C	3	4	1	2
D	2	3	4	1

• Each direction (N, E, S, W) is assigned to a unique time slot (1–4) per ancilla, with the fifth slot available for idle or for boundary constraint satisfaction.
• A 2×2 checkerboard tiling of pattern assignments (A–D) prevents conflicts—no two ancillas ever attempt to use the same data qubit in the same slot.
• At seams between codewords, the idle (fifth) slot allows shifting CNOTs to enforce stabilizer precedence.

This structured scheduling maintains local parallelism, satisfies constraints, and enables effective hook-error avoidance across the fused code surface.

4. Stabilizer Circuit Formulation and Error Propagation

Stabilizer generators supported on face $f$ are

$$S_f^Z = \prod_{i \in f} Z_i, \qquad S_f^X = \prod_{i \in f} X_i$$

The corresponding measurement (syndrome extraction) circuits in the Heisenberg picture:

• Z-type:

$$M_Z(f) = \left( \bigotimes_{i \in f}\mathrm{CNOT}(i \to a) \right)~|0\rangle_a\langle 0|$$

• X-type:

$$M_X(f) = \left( \bigotimes_{i \in f}\mathrm{CNOT}(a \to i) \right)~|+\rangle_a\langle +|$$

Hook errors arise from a single ancilla Pauli error $E_a$ between its $k$-th and $(k+1)$-th CNOTs; for instance, $E_a = X_a$ propagates as $X_{i_k} X_{i_{k+1}}$.

Thus, designating which pairs of CNOTs can be sequential in a stabilizer’s personal schedule is crucial to suppress logical errors caused by fault propagation.

5. Error-Rate Performance and Space Overhead

Monte Carlo simulations at the circuit level, using depolarizing noise rate $p$ for two-qubit gates, measurement, and initialization (with $p/10$ on single-qubit gates and idles), yield the following results for central logical qubits in a 5-patch dense fusion (with pymatching decoding):

• Four-slot, non-hook-avoiding dense scheduling results in higher logical error rate than the standalone patch arrangement for all code distances $d \leq 11$.
• Five-slot, pattern-A–D hook-avoiding schedule achieves logical error rate matching the standalone code at $p\approx 10^{-2}$, and outperforms standalone for $p \lesssim 5 \times 10^{-3}$ once $d \geq 7$.
• At $d=11$ and $p=10^{-3}$, hook-avoiding dense scheduling yields a logical error per round of $\sim 1 \times 10^{-5}$ (vs. $\sim 3 \times 10^{-5}$ for standalone).

The procedure thus enables simultaneous reduction of physical qubit overhead (to approximately $3/4$ per logical qubit relative to unfused patches) and preservation (or improvement) of effective code distance at noise rates relevant to near-term fault-tolerant quantum computing.

6. Pseudocode for Scheduler Implementation

The scheduling protocol may be encoded as:

for round in range(d): # 1) initialize ancillas for a in ancillas: if a.type == 'Z': init_z(a) else: init_x(a) # 2) five CNOT steps for t in [1,2,3,4,5]: for a in ancillas: for (dir, q) in neighbour_map[a]: slot = dir2slot[dir] # 1..4 # in dense code we leave t=5 as idle if t == slot: if a.type == 'Z': CNOT(data=q, anc=a) else: CNOT(anc=a, data=q) # 3) measure ancillas for a in ancillas: if a.type == 'Z': meas_z(a) else: meas_x(a) # 4) feed measurements into decoder

Pattern assignment in a 2×2 checkerboard ensures no CNOT contention. At patch seams, the fifth (idle) slot enables proper shifting of CNOT blocks to guarantee stabilizer precedence. This protocol recovers hook-error-avoiding behavior and dense code benefits as demonstrated in simulation.

7. Significance and Practical Implications

CNOT gate-scheduling for stabilizer measurement, as described, is a practical enabler for high-density, fault-tolerant quantum architectures based on the surface code. By combining local contention avoidance, stabilizer precedence, and hook-error suppression, the methodology ensures the simultaneous maintenance of logical error rate and reduction of physical qubit demand. These results demonstrate that dense surface code packing with proper syndrome extraction protocols does not fundamentally compromise code effectiveness, and, for sufficiently large distances and favorable noise rates, offers improved logical protection relative to conventional layouts (Fujiu et al., 10 Nov 2025). This scheduling strategy is thus a central component for scalable quantum error correction in resource-constrained platforms.