Chip@k: Multi-Domain Chip Analysis

• Chip@k is a multifaceted concept that defines labeled chip-firing on k-ary trees, top-k hardware evaluation metrics, and chiplet-system design challenges.
• In combinatorics, it uses a deterministic chip-firing process with base-k digit routing to generate stable permutations with exact inversion and descent properties.
• In hardware and chiplet contexts, Chip@k quantifies design success probabilities and frames cross-layer optimization problems to improve PPA and overall system performance.

Chip@k is used in recent arXiv literature in multiple technically distinct ways. In combinatorics, it denotes a family of labeled chip-firing constructions on infinite rooted directed $k$-ary trees, where $k$ simultaneously fixes tree arity, firing threshold, and the base-$k$ structure of chip labels, and where the terminal layer can be read as a permutation (Inagaki et al., 12 Mar 2025). In automated hardware design, it denotes a probabilistic top-$k$ acceptability metric for LLM-generated accelerator designs under joint power, performance, and area constraints (Nazzal et al., 23 Jul 2025). In chiplet-system design, the term also appears more loosely as shorthand for large cross-layer chip/chiplet optimization problems rather than a single formal metric or transform (Wu et al., 20 Apr 2026).

1. Terminological scope

The coexistence of several meanings is central to the modern usage of Chip@k. The combinatorial meaning is rooted in chip-firing theory on $k$-ary trees. The hardware-evaluation meaning is modeled on hit-rate-style top-$k$ metrics and is explicitly tied to PPA-qualified design generation. The chiplet-systems usage treats “Chip@k” as a scale marker for design spaces involving many chips, chiplets, packaging choices, and workload constraints.

Context	Meaning of Chip@k	Representative source
Combinatorics	Labeled chip-firing on directed $k$-ary trees	(Inagaki et al., 12 Mar 2025)
Hardware design evaluation	Probability that at least one of $k$ sampled designs is PPA-acceptable	(Nazzal et al., 23 Jul 2025)
Chiplet-system optimization	Cross-layer chip/chiplet design-at-scale problem framing	(Wu et al., 20 Apr 2026)

Disambiguation is therefore essential. In the combinatorial literature, Chip@k is a structured dynamical system with exact theorems on stable configurations, inversions, descents, and landing ranges. In hardware-design literature, Chip@k is an evaluation functional over sampled candidate designs. The two notions share the symbol “@$k$” and an output-selection semantics, but they arise from different mathematical objects and answer different questions.

2. Directed $k$-ary tree chip-firing model

In the directed-tree formulation, the underlying graph is an infinite rooted directed $k$0-ary tree with a distinguished root $k$1, indegree $k$2 at every non-root vertex, outdegree $k$3 at every vertex, and linearly ordered children from leftmost to rightmost. Layers are numbered with the root on layer $k$4. For integers $k$5 and $k$6, the standard initial state places $k$7 labeled chips at the root. One convention labels them $k$8, padding each label to a length-$k$9 base-$k$0 string; a closely related convention uses labels $k$1 (Inagaki et al., 12 Mar 2025, Inagaki et al., 25 Jun 2025).

A vertex can fire when it has at least $k$2 chips. In the basic labeled rule, one selects exactly $k$3 chips, orders them by label, and sends the smallest to child $k$4, the next to child $k$5, and the largest to child $k$6. Because every firing moves chips strictly downward and the initial chip count is exactly $k$7, the unlabeled terminal profile is rigid: the unique stable unlabeled configuration has exactly one chip on each vertex of layer $k$8 and zero chips elsewhere. Reading those $k$9 terminal chips from left to right produces a permutation of the label set (Inagaki et al., 12 Mar 2025).

This model admits a natural base-$k$0 interpretation. If a label $k$1 is written as

$k$2

then the digit positions $k$3 serve as routing resources. A permutation $k$4 assigns one digit position to each layer. Under the strategy $k$5, every vertex on layer $k$6 sends a chip to its $k$7-st child exactly when the chip’s $k$8-th base-$k$9 digit is $k$0. Thus the path of a chip is determined by its digits and the order in which the strategy consumes those digits (Inagaki et al., 12 Mar 2025).

The terminal configuration is therefore not merely stable; it is a deterministic routing image of the initial label set under a levelwise digit-selection protocol. This is the sense in which Chip@k acts as a combinatorial transform.

3. Permutation transform, Lehmer codes, and exact statistics

The permutation-based formulation of Chip@k defines a map

$k$1

where $k$2 is the permutation obtained by listing the terminal-layer chip labels from left to right. The routing proposition is explicit: if $k$3 is a traversal string with $k$4, then the chips reaching the vertex $k$5 are exactly those with digits satisfying

$k$6

For $k$7, there is exactly one such chip, so the terminal layer is in bijection with base-$k$8 digit strings reordered by $k$9 (Inagaki et al., 12 Mar 2025).

A central result is that standard permutation statistics of $k$0 are governed by the Lehmer code $k$1 of $k$2. If $k$3 denotes the inversion count of the terminal permutation, then

$k$4

This yields several structural consequences. The identity permutation $k$5 gives $k$6, hence a fully sorted terminal configuration. The decreasing permutation $k$7 attains the global maximum

$k$8

For all $k$9, $k$0, and $k$1, the inversion count is divisible by

$k$2

In the binary case, the possible inversion counts are exactly

$k$3

so the inversion spectrum is a full arithmetic progression (Inagaki et al., 12 Mar 2025).

Descents are equally structured. If $k$4, then the descent number is

$k$5

The descent set itself is characterized by base-$k$6 expansions of terminal-layer indices: a position is a descent exactly when the last nonzero digit of its index lies in $k$7. One corollary is that every descent index is divisible by $k$8, so the only possible descent positions are

$k$9

The map $k$0 is also injective. The lexicographic comparison theorem shows that distinct strategies $k$1 produce distinct stable configurations, so a “small” permutation in $k$2 is embedded without collisions into a highly structured permutation of length $k$3 (Inagaki et al., 12 Mar 2025).

4. Related combinatorial generalizations

The permutation-strategy model sits within a broader directed-tree chip-firing program. One complementary line of work asks not which permutation statistics arise from a fixed routing strategy, but which chip labels can land at which terminal vertices under arbitrary legal firings. For a terminal vertex $k$4 with traversal string $k$5, the set of attainable labels is exactly the interval

$k$6

Every label in this interval can appear at $k$7, and no label outside it can. The length of this landing range is

$k$8

If $k$9 is odd, every such length is odd; if two traversal strings are permutations of one another, then they have the same landing range (Inagaki et al., 25 Jun 2025).

A dual chip-centric description is also available. A chip labeled $k$0 can land at exactly those vertices whose traversal strings satisfy

$k$1

The leftmost and rightmost attainable terminal vertices are given explicitly from the leading base-$k$2 digits of $k$3 and $k$4. This yields exact formulas for a chip’s spread across the terminal layer, with extremal behavior depending sharply on $k$5 (Inagaki et al., 25 Jun 2025).

Earlier directed-tree work counted all reachable stable labeled configurations from $k$6 chips at the root. If $k$7 denotes that count and $k$8 is the $k$9-dimensional Catalan number, then

$k$0

That same work identified a distinguished stable permutation $k$1 obtained by repeated unbundling and proved that $k$2 equals the radix-$k$3 digit-reversal permutation $k$4. Among all stable permutations, $k$5 has the maximum number of inversions (Inagaki et al., 2024).

The directed model is not the only extension. On undirected looped $k$6-ary trees with

$k$7

labeled chips initially at the root, recent work established an endgame poset, proved endgame confluence, generalized binary-tree smallest/largest-chip location results to arbitrary $k$8, and derived a zigzag upper bound and a constructive lower bound on the number of stable labeled configurations (Inagaki et al., 22 Sep 2025). This suggests that the combinatorial Chip@k program now spans a family of related directed and undirected $k$9-ary-tree models rather than a single isolated construction.

A distinct unlabeled baseline uses an infinite $k$00-ary tree with a self-loop at the root and threshold $k$01. There the final stable configuration is described layerwise by the base-$k$02 digits of

$k$03

and the root odometer satisfies

$k$04

Although this is a different model, it supplies a useful abelian background for the labeled variants (Agrawal et al., 12 Jan 2025).

5. Chip@k as a hardware-design evaluation metric

In FedChip, Chip@k is not a chip-firing process but a top-$k$05 success probability for LLM-generated accelerator designs. The underlying supervised dataset is

$k$06

where each prompt $k$07 is paired with a ground-truth hardware design $k$08 annotated by three PPA metrics: AREA, SLACK, and POWER. Given a prompt $k$09, the model generates a design $k$10; after synthesis and PPA extraction, deviations are computed against the reference design, e.g.

$k$11

For each metric $k$12, the paper forms the empirical distribution of ground-truth values, computes its standard deviation $k$13, and accepts a generated candidate on that metric if $k$14. A design is acceptable only if all three predicates pass simultaneously. The paper motivates the one-sigma criterion via the Three Sigma Rule and states that

$k$15

If $k$16 acceptable designs are found among $k$17 generated candidates for description $k$18, then

$k$19

The hypergeometric term is the probability that none of the $k$20 sampled candidates is acceptable, so Chip@$k$21 is the probability that at least one is acceptable. For $k$22,

$k$23

so Chip@1 is the average fraction of acceptable candidates (Nazzal et al., 23 Jul 2025).

FedChip uses this metric to compare centralized fine-tuning, federated fine-tuning, and independent local training on APTPU-Gen, a dataset of 30k design variations. Reported Chip@1 values are $k$24 for centralized training, $k$25 for the federated model, and $k$26, $k$27, and $k$28 for the three independently trained clients. The paper also states that FedChip “outperforms the highest performing vanilla LLM (GPT-o1) by around 77%” under this PPA-qualified acceptability criterion. In this usage, Chip@k is explicitly a constraint-aware analog of Hit@k or pass@k, specialized to hardware design generation (Nazzal et al., 23 Jul 2025).

6. Cross-layer chiplet design and conceptual distinctions

A third usage appears in work on 2.5D and 3D chiplet-based systems, where “Chip@k problems” denotes large cross-layer design spaces involving application mapping, architecture, chiplet parameters, and package technology. CHICO-Agent formalizes this as optimization over a configuration vector $k$29 and minimizes a weighted system cost

$k$30

with $k$31, $k$32, $k$33, and $k$34 denoting energy, area, latency, and manufacturing cost. The framework uses an admin–field multi-agent workflow, a persistent/evolving knowledge base, and analytical PPAC models derived from CarbonPATH. Across 24 workload/profile combinations, CHICO-Agent achieves lower cost than a simulated-annealing baseline in 20 cases (Wu et al., 20 Apr 2026).

This usage is conceptually adjacent to FedChip’s metric but formally different. FedChip’s Chip@k is an evaluator over sampled generated designs. CHICO-Agent instead addresses search and reasoning over cross-layer design spaces, with “Chip@k” functioning as a design-at-scale problem framing. The combinatorial Chip@k literature is different again: there the object of study is a deterministic or strategy-dependent chip-firing transform on $k$35-ary trees, with exact structural theorems on stable configurations and permutation statistics. Recent arXiv usage therefore supports no single canonical definition of Chip@k; rather, the term denotes a family of $k$36-indexed constructions whose common feature is controlled selection among many chip-related outcomes, but whose mathematical content depends entirely on context (Wu et al., 20 Apr 2026).

In that sense, Chip@k now names three research programs. One is algebraic-combinatorial, centered on labeled chip-firing, base-$k$37 routing, and permutation structure. One is evaluative, centered on probabilistic top-$k$38 acceptability under multi-objective PPA constraints. One is systems-oriented, centered on cross-layer chip/chiplet exploration. Their notation overlaps, but their state spaces, objectives, and invariants are distinct.