BA+: Augmented Bitcell Array for In-Memory Compute

• BA+ is an augmented SRAM architecture that integrates bitcell-level and array-level enhancements to boost storage density and enable flexible in-memory computation.
• It employs dual-bit and ternary-storage cells with dynamic modes, allowing run-time trade-offs between accuracy, latency, and energy efficiency.
• BA+ incorporates analog compute-in-memory primitives using support parameters, enabling efficient MAC operations with minimal area and power overhead.

The Augmented Bitcell Array (BA⁺) architecture refers to a class of SRAM-based array designs that extend conventional bitcell functionality to enable enhanced storage density, flexible computation, and in-memory computing primitives. BA⁺ achieves these features through augmentations either at the bitcell level (e.g., dual/multibit dynamic storage) or at the array level (e.g., blockwise linear parameter augmentation for binarized neural network weights), allowing run-time trade-offs in accuracy, latency, and memory footprint. This architecture subsumes both circuit-level innovations—such as dynamic mode memory cells capable of hybrid SRAM/DRAM storage—and algorithmic mechanisms for flexible neural network inference and training on in-memory platforms (Nasrin et al., 2019, Sheshadri et al., 2021).

1. Core BA⁺ Concepts: Augmented Functionality in SRAM Arrays

BA⁺ schemes introduce two major categories of augmentation:

• Bitcell-level augmentation: Enables each SRAM cell to store more than one bit by overlaying a dynamic storage node alongside conventional static SRAM bits. Typical implementations include 8-transistor (8T) dual-bit and 7-transistor (7T) ternary-storage cells, each operating in "Normal" or "Augmented" mode (Sheshadri et al., 2021).
• Array-level augmentation: Integrates real-valued "support parameters" into memory-level computation flows, as in BA⁺-supported binary neural network (BNN) inference. These parameters enable blockwise, tunable expansion of the effective weight space beyond native binarized storage, with minimal hardware overhead (Nasrin et al., 2019).

This dual perspective positions BA⁺ as an architectural generalization encompassing both memory capacity enhancements and compute-in-memory accuracy/latency trade-offs.

2. Detailed Architecture and Mathematical Formalism

2.1 Bitcell Augmentation: 8T Dual-Bit and 7T Ternary Cells

• 8T dual-bit cell in BA⁺:
  • Normal mode: Functions as a conventional 6T cell with cross-coupled inverters, storing a single static bit, accessed via WL1 and WL2.
  • Augmented mode: Adds a dynamic (DRAM-like) storage node, accessible via an additional wordline (WL2), so a single cell simultaneously stores both a static and a dynamic bit.
• 7T ternary-storage cell:
  • Normal mode: Conventional 6T behavior.
  • Augmented mode: Feedback via header PMOS is removed, and two internal nodes function as high-retention dynamic nodes capable of storing three possible states, i.e., ternary information.

2.2 BA⁺ Support Parameters for BNNs

The BA⁺ array partitions each weight matrix $W \in \{-1, +1\}^{m \times n}$ into blocks $B_{i,j}$ ($p \times 1$). For each block, the architecture stores two real-valued support parameters $(a_{i,j}, b_{i,j})$. Inference modifies each binary weight $w$ as:

$$w^+ = a_{i,j} \cdot w + b_{i,j}, \qquad w \in \{-1, +1\}$$

The effective weight space per block consequently broadens to $[ -a_{i,j} + b_{i,j},\; +a_{i,j} + b_{i,j} ]$. At runtime, block support parameters are loaded into the row-DAC buffer, which modulates the per-block bias current and offset in the analog domain during the in-memory computing flow.

2.3 Array Layout and Data Flow

A typical BA⁺ sub-array includes:

• Row decoders for mode selection (Normal/Augmented)
• Bitline precharge, sense amplifiers (differential or single-ended)
• Mode control register and refresh controller for dynamic bit maintenance
• Compute-in-memory (CIM) MAC or accumulator logic for BNN-support parameters

3. Compute-in-Memory Flow and Dynamic Trade-offs

BA⁺ supports a modified Compute-in-Memory (CIM) workflow:

1. Precharging and blockwise activation of bitcell rows
2. Digital-to-analog conversion via a row DAC, with per-block scaling and offset by ($a_{i,j}$, $b_{i,j}$)
3. Per-cell current direction and magnitude determined by the stored binary $w^b_{r,c}$ and block supports
4. Blockwise column current accumulation and ADC digitization
5. Downstream digital accumulation and activation computation

In BA⁺-BNN, a "dynamic dropout" mechanism is introduced: at runtime, a configurable fraction $B_{i,j}$0 of block supports may be skipped by setting $B_{i,j}$1, using only the unaugmented $B_{i,j}$2 result for those blocks. This yields a direct, tunable trade-off between inference latency/energy and accuracy. Specifically, for MNIST (4-bit support), test accuracy fits

$B_{i,j}$3

With up to 52% supports dropped, test accuracy remains within 0.2% of the baseline (Nasrin et al., 2019).

4. Capacity, Density, and Hardware Overhead

Cell Type	Storage (Normal)	Storage (Augmented)	Area Overhead
6T (baseline)	1b/static	N/A	—
8T (BA⁺)	1b/static	2b (1 static, 1 dynamic)	~30%
7T (BA⁺)	1b/static	$B_{i,j}$4 ($B_{i,j}$51.585b)	~20%

• At 22 nm FDX, the 8T dual-bit cell offers up to 2× memory density; the 7T ternary cell enables a 1.6× increase. Area penalties remain in the 20–40% range.
• Access time in augmented mode is higher due to dynamic bit sensing. For the 8T dynamic bit: $B_{i,j}$6 ns; for 7T ternary: $B_{i,j}$7 ns.
• Power overhead for BA⁺ cells is moderate: e.g., 8T cell static read $B_{i,j}$8 fJ, dynamic $B_{i,j}$9 fJ, compared to $p \times 1$0 fJ for 6T.

In BA⁺ arrays with integrated computation, the full per-layer pass latency is approximately

$p \times 1$1

for a block size $p \times 1$2 (includes analog multiply, ADC plus digital accumulation) (Nasrin et al., 2019).

5. Refresh, Reliability, and Process Variation

Dynamic bits in BA⁺-augmented cells require periodic refreshes determined by their retention time ($p \times 1$3):

• 8T dynamic: $p \times 1$4 at $p \times 1$5
• 7T dynamic: $p \times 1$6 at $p \times 1$7

Typical refresh periods (20–250 kHz) fit within the operational envelope of deep-learning and streaming workloads. Reliability of BA⁺ is further characterized by process-variability-aware simulations. For 8T cells with a threshold voltage spread $p \times 1$8 mV, the scalar product current's standard deviation remained under 2% of nominal, and end-to-end accuracy on MNIST degraded by less than 0.2 percentage points (Nasrin et al., 2019).

6. Empirical Performance and Application Domains

In BA⁺-BNN on MNIST:

Model	Top-1 Accuracy (%)	Error Rate (%)	Error Reduction (%)
Baseline 1-bit (SRAM)	98.6	1.4	—
BA⁺ (pretrained)	99.24	0.76	35.7
BA⁺ (random init)	98.87	1.13	19.3

Throughput per 64×64 bank is $p \times 1$966 MMAC/s at 1 GHz; energy per full MNIST inference is $(a_{i,j}, b_{i,j})$01.2 μJ. Dynamic dropout of 50% support blocks can reduce energy by 40% with less than 0.2% accuracy loss.

BA⁺ arrays enable fusion of memory expansion and in-memory computation. Dual-bit and ternary capacities directly benefit workloads with memory bottlenecks—such as DNN accelerators—while the BA⁺-BNN paradigm provides tunable coverage between area/latency-optimized and accuracy-optimized inference regimes (Nasrin et al., 2019, Sheshadri et al., 2021).

7. Integration Principles and Advanced Use Cases

BA⁺ tiles are integrated through sub-array mode registers, which select between static (Normal) and hybrid or dynamic (Augmented) operation per workload section. Extra wordlines/gates are asserted as needed, and dynamic bits are initialized at mode switches.

BA⁺ is compatible with standard X-SRAM and analog compute-in-memory (IMC) techniques. The "hybrid SRAM+DRAM" memory footprint provides complete run-time flexibility—banks can swap between leakage-minimized normal mode and high-density compute-augmented mode. During augmented operation, both static and dynamic bits in 8T cells feed bit-serial CIM dot-product engines, realizing in-place accumulation or fused IMC primitives.

In summary, BA⁺ merges memory capacity scaling with robust in-memory compute paradigms, affording unique, fine-grained tunability for data-intensive, latency-constrained, and energy-aware digital systems (Sheshadri et al., 2021, Nasrin et al., 2019).