Asymmetric Tile Buffering (ATB) in GEMM

• Asymmetric Tile Buffering (ATB) is a tiling strategy for GEMM that decouples input and output tile dimensions to enhance arithmetic intensity and throughput.
• Performance models demonstrate that ATB can achieve up to 4.54× speedup over symmetric tiling, as evidenced by case studies on AMD’s XDNA2 AI Engine.
• ATB optimizes buffer utilization by balancing the trade-offs between higher arithmetic intensity and increased kernel switching overhead.

Asymmetric Tile Buffering (ATB) is a tiling strategy for general matrix multiplication (GEMM) that decouples the dimension of buffered input $A$ tiles along the $M$ axis from the dimension of output $C$ tiles, permitting significant enhancements in arithmetic intensity and overall throughput. Introduced in the context of accelerating AI workloads, ATB provides a methodical means to optimize buffer utilization in manycore and array architectures by exploiting a previously overlooked asymmetry in input/output operand buffering. Systematic performance modeling reveals that ATB can offer substantial real-world speedup over conventional symmetric tiling, as established in a detailed case study on AMD’s XDNA2 AI Engine (Wang et al., 20 Nov 2025).

1. Definition and Formulation

In symmetric GEMM tiling, a single set of tile dimensions $(T_M,T_K,T_N)$ governs the size of buffered blocks for $A$, $B$, and $C$:

• $A$-tiles are $T_M \times T_K$,
• $B$-tiles are $M$0,
• $M$1-tiles are $M$2.

Asymmetric Tile Buffering introduces four distinct tile parameters:

• $M$3: rows of $M$4 buffered,
• $M$5: rows of $M$6 buffered,
• $M$7: reduction-dimension tile size,
• $M$8: columns of $M$9/$C$0 buffered,

with the constraint $C$1. The asymmetry ratio is defined as

$C$2

which quantifies how many output rows are accumulated per input row loaded. Figure 1 in (Wang et al., 20 Nov 2025) illustrates the structural difference between symmetric tiling and ATB.

2. Performance Model and Analytical Framework

The mathematical performance model comprises several core metrics:

Arithmetic Intensity ($C$3):

Let $C$4, $C$5, $C$6 denote per-element bytes of $C$7, $C$8, $C$9 (e.g., for BF16, $(T_M,T_K,T_N)$0), and $(T_M,T_K,T_N)$1 the global reduction length. For output-stationary scheduling: $(T_M,T_K,T_N)$2

$(T_M,T_K,T_N)$3

Substituting $(T_M,T_K,T_N)$4 and simplifying gives: $(T_M,T_K,T_N)$5

This is subject to the L1 buffer constraint: $(T_M,T_K,T_N)$6

Kernel-Switching Overhead:

With a microkernel switching cost $(T_M,T_K,T_N)$7,

$(T_M,T_K,T_N)$8

Combined Throughput:

Let $(T_M,T_K,T_N)$9 be the peak per-core MAC rate and $A$0 the microkernel efficiency.

$A$1

$A$2

32-core throughput is bounded by

$A$3

3. Trade-offs and Design Space

ATB’s principal trade-off is between maximized arithmetic intensity and increased kernel switching overhead:

• High $A$4, small $A$5: Favors greater arithmetic intensity and memory reuse but exacerbates switching overhead and reduces microkernel efficiency due to shorter steady phases.
• Low $A$6, large $A$7: Improves core efficiency by yielding longer microkernel chains and fewer invocations, but at the expense of attainable arithmetic intensity.

The optimal configuration lies where buffer, compute, and switching costs are jointly minimized. This point is quantitatively determined by jointly satisfying constraints and optimizations in equations (1), (9), (11), and (12) from the analytical model.

4. Parameter Selection Guidelines

For effective deployment of ATB, the following process is recommended:

1. Choose $A$8: Select a $A$9 large enough that microkernel efficiency $B$0–$B$1 (see Table 1).
2. Increase $B$2: Grow the asymmetry ratio until switching overhead or total buffer capacity becomes the limiting factor.
3. Buffer Allocation: Allocate available buffer to maximize $B$3, thus enlarging the “memory reuse volume” and boosting $B$4.
4. Full Array Evaluation: Simulate array-level performance; if memory-bound, consider higher $B$5; if compute-bound, adjust by increasing $B$6 or reducing $B$7.

Table 1. Microkernel/core performance under Config 1, $B$8, $B$9:

$C$0	$C$1	$C$2 (TF)	$C$3
8	1	0.36	0.156
8	4	0.36	0.134
32	4	0.75	0.312
64	4	1.16	0.511

5. Practical Implementation and Architectural Case Study

ATB’s effectiveness was demonstrated on AMD’s XDNA2 AI Engine comprising 32 compute cores (4 × 8), each core with 64 KB L1 and two input/output streams. The studied GEMM used mixed-precision (BFP16/BF16) with the following configuration (Config 1, Table 3):

• Problem Size: $C$4
• L1 Tile: $C$5, $C$6
• Buffer Used: $C$7 KB (vs. 91 KB if symmetric)
• Measured Throughput: $C$8 TFLOPS/core × 32 cores = $C$9 TFLOPS (compute limit)
• Arithmetic Intensity (array): $A$0 op/B (memory limit: $A$1 TFLOPS)
• Final Throughput: $A$2 TFLOPS
• Speedup: $A$3 (baseline MLIR-AIE symmetric tiling achieves $A$4 TFLOPS)

Table 3. Impact of ATB on throughput:

L1 tile $A$5	$A$6	$A$7 (TF)	Speedup
$A$8 (symmetric)	1	4.8	1.00×
$A$9	1	17.3	3.61×
$T_M \times T_K$0	4	24.3	4.54×

Table 3 and additional configurations (see (Wang et al., 20 Nov 2025), Table 3) confirm 2–3× throughput gains across other precisions. ATB enlarges the feasible $T_M \times T_K$1 memory reuse volume, often doubling or tripling arithmetic intensity in fixed scratchpad resources.

6. Practical Considerations and Implementation

ATB is a minor extension to standard tiling loops for GEMM: only $T_M \times T_K$2 rows of $T_M \times T_K$3 are buffered while accumulation to $T_M \times T_K$4 rows of $T_M \times T_K$5 proceeds. This increased reuse of the $T_M \times T_K$6 tile directly leverages buffer capacity for enhanced output accumulation, enabling larger $T_M \times T_K$7 without surpassing scratchpad constraints. ATB is particularly beneficial under tight buffer budgets or on architectures that can tolerate moderate kernel switching overheads.

A plausible implication is that architectural features such as hardware support for fast context switching and flexible buffer management can further amplify the benefits of asymmetric tile buffering in practice. However, performance gains are contingent on careful tuning of buffer, reduction, and output tile parameters as prescribed by the performance model (Wang et al., 20 Nov 2025).