AIWC Features: Architecture-Independent Metrics

Updated 25 May 2026

AIWC features are a suite of architecture-independent metrics that quantify computational, memory, control-flow, and parallelism characteristics in OpenCL kernels.
They employ IR-level simulation to generate reproducible profiles that support performance modeling, device suitability analysis, and optimization guidance.
The metrics inform device selection and performance tuning by predicting execution times and identifying optimization opportunities like improved memory locality and load balancing.

AIWC ("Architecture-Independent Workload Characterization") refers to a suite of metrics and methodologies designed to characterize application workloads (especially OpenCL kernels) in a manner that is independent of hardware architecture details. Unlike device- or architecture-dependent profiling, AIWC features aim to quantify the inherent computational, memory, parallelism, and control-flow properties of codes. This approach enables performance modeling, device suitability analysis, and optimization guidance across a wide variety of hardware, including CPUs, GPUs, FPGAs, and MICs. In the high-performance computing (HPC) domain, AIWC has been implemented as a plugin for the Oclgrind OpenCL simulator, producing reproducible, architecture-agnostic metrics that have demonstrated predictive power for execution time and optimization potential (Johnston et al., 2018, Johnston et al., 2018, Chilukuri et al., 2020).

1. Metric Categories and Definitions

AIWC metrics are systematically divided into four primary categories: Compute, Parallelism, Memory, and Control. Each category comprises both basic counts and higher-order statistics. The following table summarizes the principal metrics, all of which are extracted from the LLVM intermediate representation (IR) of OpenCL kernels during simulated execution (Johnston et al., 2018, Johnston et al., 2018):

Category	Metric Name	Definition / Formula (where precise)
Compute	Opcode Diversity	Number of unique opcodes to cover 90% of dynamic instruction stream
	Total Instruction Count	Total dynamic instructions executed
Parallelism	Work-items	Total OpenCL threads launched
	Total Barriers Hit	Max number of barriers any thread encounters
	Instructions-to-Barrier (ITB)	Min/Median/Max instructions executed between barriers
	Instructions-per-Thread (IPT)	Min/Median/Max instructions per work-item
	SIMD Width Metrics	Max/Mean/SD of SIMD width per vector instruction
Memory	Total Memory Footprint	Unique memory addresses touched
	90% Memory Footprint	Unique addresses accounting for 90% of accesses
	Global Memory Address Entropy	$H_{global}=-\sum_j \frac{f_j}{N}\log_2\left(\frac{f_j}{N}\right)$
	Local Memory Address Entropy	Entropy after dropping $k$ LSBs: $H_{local(k)}$
Control	Total Unique Branch Instructions	Number of static branch sites executed
	90% Branch Instructions	Static branches covering 90% of dynamic branches
	Yokota Branch Entropy	Per-branch Shannon entropy over taken/not-taken history
	Average Linear Branch Entropy	$E_{lin}(i)=2\min(p_i,1-p_i)$ , averaged over branches

These metrics can be extended; for example, (Chilukuri et al., 2020) adds the Parallel Spatial Locality (PSL) metric to capture the simultaneous memory access locality across threads, addressing deficiencies of per-thread locality.

2. Architectural Independence and Implementation

AIWC achieves architectural independence by collecting data exclusively from IR-level simulation rather than hardware counters or device-specific features. Oclgrind simulates idealized hardware: perfect branch prediction, unlimited compute units, and ideal memory with no caches or pipeline effects. No measurements depend on actual device attributes such as cache sizes, pipeline depths, instruction latencies, or real-world timing (Johnston et al., 2018). This design ensures that each metric reflects only the code's structural and behavioral properties.

Technically, AIWC operates via callbacks within Oclgrind for every relevant event: instructionExecuted for instructions, memoryLoad/memoryStore for memory accesses, and synchronization events for barriers. Memory-access traces are aggregated per work-group and per timestamp to facilitate both per-thread and parallel metrics. At the end of simulation, AIWC outputs deterministic, reproducible metrics for observed code/input pairs (Johnston et al., 2018, Chilukuri et al., 2020).

3. Memory Access and Locality Metrics

In addition to traditional memory metrics (footprint, entropy), (Chilukuri et al., 2020) introduces the Parallel Spatial Locality (PSL) metric, defined as the average entropy of coarse-grained, timestamped simultaneous addresses accessed by threads within a work-group. For each timestamp $t$ and bin size $n$ (LSBs dropped), the entropy $H_n(t)$ of bins is computed over all active threads, and PSL $_n$ is the average over $t$ . Rapid decay of PSL $_n$ with $k$ 0 reflects high spatial clustering—beneficial for cache and memory coalescing. Flat PSL curves signal lack of parallel access locality, indicating potential for optimization by tiling, shared-memory buffering, or data rearrangement (Chilukuri et al., 2020).

Benchmarks reveal that classic AIWC metrics (footprint, entropy) may not distinguish all optimization strategies, while PSL can detect subtle improvements (e.g., tiling plus bank-conflict avoidance in GPU-optimized matrix-multiply kernels).

4. Control-Flow, Synchronization, and Parallelism Features

Control-flow characterization includes unique branch site counts, dynamic frequency ("90% branch instructions"), and two entropy measures: Yokota branch entropy (full taken history) and linear branch entropy (as defined in Ebrahimi et al.). These metrics quantify the predictability of control flow, critical for mapping kernels efficiently onto SIMD or SIMT hardware. High branch entropy indicates divergence, which penalizes performance on wide-vector hardware.

Parallelism is further characterized by the count of work-items, analysis of synchronization (barrier frequency and variance), and SIMD width statistics. Large variation in instruction counts between barriers or among threads highlights potential load imbalance or synchronization bottlenecks (Johnston et al., 2018). These features are vital for device suitability assessment: memory-bandwidth-sensitive workloads (high entropy, large footprint) suit architectures with wide DRAM interfaces, while highly divergent control flow favors scalar CPUs over SIMT GPUs.

5. Performance Modeling and Optimization Guidance

AIWC metrics are designed to enable predictive modeling across architectures. (Johnston et al., 2018) demonstrates that feeding the full AIWC metric vector into a Random Forest regressor yields execution time predictions with ~1.2% mean absolute error across 15 diverse CPU/GPU/MIC devices. No explicit feature selection is needed; high model stability under "leave-one-kernel-out" retraining indicates the relevance of virtually all metrics.

Metrics also inform optimization. High global memory entropy suggests optimizing data locality, a wide gap between min/max ITB indicates load imbalance, and high branch entropy encourages re-writing with predicated instructions or lookup tables. Slow decay of local memory entropy with block size suggests the need for blocking/tiling transformations. PSL provides actionable evidence for parallel memory access restructuring (Johnston et al., 2018, Chilukuri et al., 2020).

6. Comparative Perspective: AIWC versus Other Characterization Paradigms

AIWC's architecture-independent approach contrasts with device-specific profilers, which capture realized performance—including effects of caches, pipelines, and hardware nuances—but cannot generalize across device classes. In contrast, AIWC metrics provide a workload "fingerprint," enabling cross-platform analysis, benchmarking, and hardware procurement optimization. This feature is particularly advantageous in heterogeneous or evolving HPC environments where hardware targets may shift.

A plausible implication is that AIWC can also serve as a front-end data source for ML-based autotuning frameworks, device-choice heuristics, and scheduling in HPC clusters—a use case validated by its ~1% error rate in device selection and runtime prediction benchmarks (Johnston et al., 2018).

7. Limitations and Future Enhancements

Current limitations include the abstraction from certain real hardware constraints—some memory bottlenecks, interconnect effects, or multi-kernel scheduling phenomena are invisible to AIWC's IR-level analysis. The PSL extension (Chilukuri et al., 2020) addresses some interpretability gaps by quantifying parallel memory access patterns, but further extensions could include richer temporal locality measures, intra-kernel phase analysis, or synchronization pattern mining.

AIWC does not yet natively support direct characterization of non-OpenCL workloads or mixed-language pipelines, although the underlying methodologies could be ported to other IRs or execution platforms with sufficient instrumentation capability.

AIWC features, as formalized in (Johnston et al., 2018, Johnston et al., 2018, Chilukuri et al., 2020), provide a reproducible, architecture-agnostic metric suite for understanding, predicting, and optimizing parallel kernels, with demonstrated utility in device-agnostic workload modeling and cross-platform HPC performance engineering.