a-SiC/SiN Heterogeneous Integration

• a-SiC/SiN heterogeneous integration is a monolithic photonic platform where amorphous SiC provides high confinement and tunability while SiN ensures ultra-low loss.
• The design employs adiabatic tapering to overcome mode mismatch, achieving an interconnection loss of 0.32 ± 0.10 dB per connection and a density improvement exceeding 4,444×.
• Enhanced thermo-optic tuning—27 times greater than SiN alone—and complementary edge and grating couplers highlight its applicability in scalable, programmable photonics and quantum circuits.

Searching arXiv for the cited heterogeneous integration papers to ground the article in the current literature. a-SiC/SiN heterogeneous integration is a monolithic photonic integration strategy in which amorphous silicon carbide (a-SiC) and silicon nitride (SiN) are combined on the same chip and connected through adiabatic interconnection couplers. In the reported implementation, SiN serves as the ultra-low-loss routing backbone, while a-SiC supplies tighter confinement, stronger thermo-optic response, and stronger third-order nonlinear functionality. The resulting platform was reported with an on-chip interconnection loss of $0.32 \pm 0.10\ \mathrm{dB}$ per a-SiC/SiN connection, an integration density increment exceeding 4,444-fold, and 27 times higher thermo-optic tuning efficiency relative to the SiN photonic platform (Li et al., 14 Jul 2025).

1. Material complementarity and integration rationale

The motivation for a-SiC/SiN heterogeneous integration is explicitly based on the complementarity of the two material platforms. SiN is described as an industrial well-established and well-matured platform with ultra-low propagation loss, a wide transparency window spanning visible to telecom wavelengths, and mature fabrication. These attributes make it suitable for low-loss routing, delay lines, resonators, and nonlinear optics. Its limitations, in the same account, are equally central: the low refractive index leads to poor confinement and therefore large bend radius, the minimal bending radius in ultra-low-loss high-aspect-ratio SiN is on the millimeter to sub-centimeter scale, and the low thermo-optic coefficient makes active tuning inefficient (Li et al., 14 Jul 2025).

a-SiC is introduced as the complementary layer. It is characterized by higher refractive index, large thermo-optic coefficient, strong Kerr nonlinearity, CMOS-compatible low-temperature CVD deposition, and the ability to be deposited on arbitrary substrates with good thickness control. These properties make it better suited for compact active elements and dense routing, while its higher optical loss than state-of-the-art SiN makes it less suitable as a pure ultra-low-loss routing backbone. The integration concept therefore assigns SiN to functions dominated by loss and a-SiC to functions dominated by compactness and tunability (Li et al., 14 Jul 2025).

A common simplification is to treat heterogeneous integration as merely a material stack. The reported work frames it instead as a division of labor between dissimilar waveguide layers, with each material used where its limitations are least consequential and its strengths are maximal. A plausible implication is that the architecture is motivated as much by PIC systems engineering as by material science.

The broader context of a-SiC heterointegration is reinforced by a separate demonstration of direct a-SiC deposition on thin-film lithium niobate, where low-temperature ICPCVD, no LN etching, and standard silicon-compatible RIE were emphasized as alternatives to transfer-bonding (Li et al., 2024). This suggests that the appeal of a-SiC extends beyond any single substrate pair and includes its role as a deposited photonic layer for foundry-compatible heterogeneous platforms.

2. Monolithic architecture and interconnection design

The a-SiC/SiN platform uses a high-aspect-ratio SiN waveguide layer for low-loss routing and a separate a-SiC waveguide layer for compact, strongly tunable, and dense functionality. The interface between them is realized through bidirectional adiabatic interconnection couplers. In the single-mode regime cited for the platform, the SiN waveguide is about $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$, whereas the a-SiC waveguide is about $260\ \mathrm{nm} \times 800\ \mathrm{nm}$. The index contrast between a-SiC and SiN is around $\Delta n \approx 0.6$ at $1550\ \mathrm{nm}$, and there is also a $160\ \mathrm{nm}$ thickness difference, producing substantial modal mismatch (Li et al., 14 Jul 2025).

To address this mismatch, both waveguides are tapered down at the coupling interface. The optimal simulated taper tip widths were reported as $w_{\mathrm{tSiC}} = 50\ \mathrm{nm}$ for a-SiC and $w_{\mathrm{tSiN}} = 2\ \mu\mathrm{m}$ for SiN, with tapering lengths denoted $L_{\mathrm{tSiC}}$ and $L_{\mathrm{tSiN}}$. The operating principle is adiabatic mode transfer from the a-SiC waveguide into the composite coupling region and then into the SiN waveguide, and vice versa (Li et al., 14 Jul 2025).

The principal interface challenge is identified not simply as lithographic alignment, but as mode mismatch. Because the two waveguide systems differ in confinement strength and vertical thickness, the design depends on adiabatic tapering on both platforms, very small final tip widths for a-SiC, and partial widening of SiN to produce a better overlap region. Fabrication tolerance was examined by sweeping $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$0 to $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$1 and $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$2 to $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$3. Over these sweeps, the maximum extra loss was only $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$4, and the a-SiC tip width had the stronger effect on performance (Li et al., 14 Jul 2025).

This emphasis on modal engineering is significant because it clarifies where the heterogeneous boundary is most vulnerable. The reported tolerance indicates that the interface is robust, but not indifferent to fabrication control. In particular, the stronger sensitivity to the a-SiC tip width indicates that the compact high-index layer sets the tighter fabrication constraint.

3. Interconnection loss, bend scaling, and density enhancement

The interconnection coupler is the enabling element of the platform. Using FDE and FDTD simulations, the work shows the mode profiles in the a-SiC waveguide, the coupling region, and the SiN waveguide. A $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$5 bend in a-SiC was also incorporated in the simulated light path to verify compact routing (Li et al., 14 Jul 2025).

The bend-radius contrast between the two platforms is central to the claimed density advantage. In simulation, the minimal bend radius in a-SiC is below $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$6, and experimentally it is inferred to be smaller than $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$7. By contrast, high-aspect-ratio SiN requires bends on the $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$8 scale. The paper formalizes integration density through bend scaling, using $100\ \mathrm{nm} \times 3\ \mu\mathrm{m}$9 and

$260\ \mathrm{nm} \times 800\ \mathrm{nm}$0

On that basis, the reported density improvement relative to high-aspect-ratio SiN-only photonics exceeds $260\ \mathrm{nm} \times 800\ \mathrm{nm}$1 (Li et al., 14 Jul 2025).

The measured interconnection loss is reported as

$260\ \mathrm{nm} \times 800\ \mathrm{nm}$2

This value was extracted by comparing structures containing two interconnection couplers and two grating couplers against reference structures with matched grating couplers but without the interconnection section. The simulation predicted that the interconnection loss could be below $260\ \mathrm{nm} \times 800\ \mathrm{nm}$3 per connection at $260\ \mathrm{nm} \times 800\ \mathrm{nm}$4 for the optimized geometry (Li et al., 14 Jul 2025).

These numbers address a recurring concern in heterogeneous PIC design: that gains in density or tunability may be nullified at the material boundary. Here, the reported boundary penalty is small enough that the combination of SiN’s low-loss routing and a-SiC’s dense active functionality remains practically meaningful. The paper explicitly frames the platform not just as a material stack, but as a practical systems-level solution.

4. Thermo-optic response and active-function partitioning

The thermo-optic comparison was performed experimentally using ring resonators in both materials on the same chip under global heating from $260\ \mathrm{nm} \times 800\ \mathrm{nm}$5 to $260\ \mathrm{nm} \times 800\ \mathrm{nm}$6. The a-SiC ring had $260\ \mathrm{nm} \times 800\ \mathrm{nm}$7 and exhibited a resonance shift of $260\ \mathrm{nm} \times 800\ \mathrm{nm}$8. The SiN ring had $260\ \mathrm{nm} \times 800\ \mathrm{nm}$9 and exhibited a resonance shift of $\Delta n \approx 0.6$0 (Li et al., 14 Jul 2025).

To account for differing resonator sizes, the work normalized tuning by waveguide length. The reported values were $\Delta n \approx 0.6$1 for a-SiC and $\Delta n \approx 0.6$2 for SiN, yielding 27 times higher thermo-optic tunability for a-SiC than SiN. The extracted thermo-optic coefficients were $\Delta n \approx 0.6$3 for a-SiC and $\Delta n \approx 0.6$4 for SiN (Li et al., 14 Jul 2025).

The thermal analysis was expressed through an effective-index perturbation model. For the resonance shift, the reported relation was

$\Delta n \approx 0.6$5

with $\Delta n \approx 0.6$6 as the thermal expansion coefficient of silica (Li et al., 14 Jul 2025).

The significance of this result is architectural rather than merely material-specific. SiN remains advantageous where accumulated passive loss dominates, whereas a-SiC becomes the preferred layer for compact tuning elements. This partitioning is particularly relevant for programmable PICs, where dense routing, many tunable elements, and low cumulative insertion loss must coexist.

5. Fiber-to-chip coupling modalities

A distinctive feature of the a-SiC/SiN platform is that it supports both edge coupling and grating coupling, with each material used where it is most favorable. On the SiN side, the work uses inverted taper edge couplers. The rationale is based on mode size: at $\Delta n \approx 0.6$7, the SMF-28 mode area is approximately $\Delta n \approx 0.6$8, the a-SiC waveguide mode area is approximately $\Delta n \approx 0.6$9, and the high-aspect-ratio SiN waveguide mode area is approximately $1550\ \mathrm{nm}$0. Because the SiN mode is larger and more weakly confined than the a-SiC mode, it is easier to match to the fiber mode (Li et al., 14 Jul 2025).

For this edge-coupling configuration, the optimal SiN taper tip width was reported as $1550\ \mathrm{nm}$1, with simulated coupling efficiency up to $1550\ \mathrm{nm}$2 per fiber-to-chip interface when the fiber gap is zero. Experimentally, two edge couplers plus a $1550\ \mathrm{nm}$3 SiN bend produced $1550\ \mathrm{nm}$4 collected output power, whereas only $1550\ \mathrm{nm}$5 was collected without tapered couplers, corresponding to a $1550\ \mathrm{nm}$6 improvement (Li et al., 14 Jul 2025).

On the a-SiC side, the work uses apodized grating couplers. The stated rationale is that the higher refractive index gives greater freedom in grating design and that a-SiC is better suited than high-aspect-ratio SiN, which is too weakly confined to make highly efficient gratings. Six grating-coupler devices were fabricated with grating period $1550\ \mathrm{nm}$7. The apodized grating line widths ranged from $1550\ \mathrm{nm}$8 to $1550\ \mathrm{nm}$9 for devices 1–3, and from $160\ \mathrm{nm}$0 to $160\ \mathrm{nm}$1 for devices 4–6. The measured maximum normalized output power was $160\ \mathrm{nm}$2 at $160\ \mathrm{nm}$3, with more than $160\ \mathrm{nm}$4 around $160\ \mathrm{nm}$5 (Li et al., 14 Jul 2025).

These complementary interfaces give the platform an additional systems-level degree of freedom. Edge coupling on SiN is favored when highest bandwidth matters, low insertion loss is needed, and chip facet access is practical. Grating coupling on a-SiC is favored when wafer-scale testability matters, alignment tolerance is important, many input/output ports are needed, and chip-facet access is undesirable. The reported platform advantage is therefore not only multimaterial routing, but multimodal external interfacing.

6. Applications, limitations, and relation to other heterogeneous platforms

The platform is explicitly positioned for programmable photonics, quantum photonics, nonlinear optics, and beyond. For programmable photonics, the claimed advantage is that SiN provides low-loss delay and routing while a-SiC provides compact and efficient tuning, which improves scalability relative to SiN alone. For quantum photonics, the cited use cases include deterministic integration of nanowire quantum dots, chip-integrated single-photon sources, on-chip quantum interference, and quantum circuits. For nonlinear optics, the work highlights four-wave mixing, frequency conversion, frequency combs, and correlated photon-pair generation (Li et al., 14 Jul 2025).

The limitations are also explicit. SiN is suboptimal for high-density reconfigurable photonics because of large minimum bending radius and constrained tunability, while a-SiC has higher optical loss than state-of-the-art SiN and is therefore less suitable as the sole low-loss backbone. At the interface, the dominant issue is mode mismatch rather than only physical alignment, and the a-SiC tip width is the more sensitive parameter in the interconnection taper design (Li et al., 14 Jul 2025).

In the wider heterogeneous-photonics landscape, a-SiC/SiN integration can be read alongside the direct deposition of a-SiC on thin-film lithium niobate. That separate platform used ICPCVD at low temperature, standard silicon-compatible reactive ion etching, intact LN, and reported ring resonators and waveguides with $160\ \mathrm{nm}$6, propagation loss $160\ \mathrm{nm}$7 for the TE mode, and TE mode tuning $160\ \mathrm{nm}$8 with $160\ \mathrm{nm}$9 (Li et al., 2024). This suggests that a-SiC is being developed as a general-purpose heterogeneous layer that can be paired either with ultra-low-loss SiN for compact tunable PICs or with LN for electro-optic and $w_{\mathrm{tSiC}} = 50\ \mathrm{nm}$0-enabled photonics.

Taken together, the reported a-SiC/SiN results define a specific heterointegration paradigm: SiN is retained where ultra-low loss and broadband transparency are decisive, a-SiC is inserted where compactness, thermal tunability, and third-order nonlinearity are decisive, and the interconnection between them is engineered so that the boundary penalty remains low. Within that framing, the platform’s reported $w_{\mathrm{tSiC}} = 50\ \mathrm{nm}$1 interconnection loss, $w_{\mathrm{tSiC}} = 50\ \mathrm{nm}$2 density improvement, and 27-fold thermo-optic tuning enhancement are the key empirical markers of its viability (Li et al., 14 Jul 2025).