Parameterized Hardware Architecture for Frame Synchronization at all Noise Levels (2501.13717v1)

Abstract: Frame synchronization is the act of discerning the first bit of a valid data frame inside an incoming transmission. This is particularly important in high-noise environments where the communication channel significantly alters transmitted signals. Sync word frame synchronization is a subcategory of synchronization methods where sync words are detected through digital correlation. Despite its simplicity, this method has been overlooked in literature in favor of more sophisticated and mathematically more optimal solutions. In this article we employ binary sync-word correlation-based synchronization to achieve near perfect frame synchronization at any noise level. The proposed architecture leverages XNOR gates, adder and comparator tree structures to detect sync words that are placed in front of the frames through digital correlation. The tree structures are circuit elements that mimic binary trees in form and provide the summation (adder tree) or the maximum/minimum (comparator tree) of a set of binary numbers as output. Due to their minimalistic nature, synchronization can be implemented practically for very large sync word sizes (>500 bit) with multigigabit bit rates (>20 Gbps) and very high accuracy (10e-5 synchronization error when the bit error rate on the bitstream is close to 0.3) on commercial FPGAs. The architecture also delivers the payload of the frames to its output as an extra function.