SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generation (2404.10875v2)
Abstract: In the ever-evolving landscape of Deep Neural Networks (DNN) hardware acceleration, unlocking the true potential of systolic array accelerators has long been hindered by the daunting challenges of expertise and time investment. LLMs offer a promising solution for automating code generation which is key to unlocking unprecedented efficiency and performance in various domains, including hardware descriptive code. The generative power of LLMs can enable the effective utilization of preexisting designs and dedicated hardware generators. However, the successful application of LLMs to hardware accelerator design is contingent upon the availability of specialized datasets tailored for this purpose. To bridge this gap, we introduce the Systolic Array-based Accelerator Data Set (SA-DS). SA-DS comprises a diverse collection of spatial array designs following the standardized Berkeley's Gemmini accelerator generator template, enabling design reuse, adaptation, and customization. SA-DS is intended to spark LLM-centered research on DNN hardware accelerator architecture. We envision that SA-DS provides a framework that will shape the course of DNN hardware acceleration research for generations to come. SA-DS is open-sourced under the permissive MIT license at https://github.com/ACADLab/SA-DS.git}{https://github.com/ACADLab/SA-DS.
- Y.-H. Chen et al., “Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks,” IEEE JSSC, vol. 52, no. 1, pp. 127–138, 2016.
- W.-Q. Ren et al., “A survey on collaborative dnn inference for edge intelligence,” Machine Intelligence Research, vol. 20, no. 3, pp. 370–395, 2023.
- H. Genc et al., “Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration,” in DAC. IEEE, 2021, pp. 769–774.
- K. Asanovic, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitz et al., “The rocket chip generator,” EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, vol. 4, pp. 6–2, 2016.
- P. Xu and Y. Liang, “Automatic code generation for rocket chip rocc accelerators,” 2020.
- R. Xu, S. Ma, Y. Wang, and Y. Guo, “Hesa: Heterogeneous systolic array architecture for compact cnns hardware accelerators,” in 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2021, pp. 657–662.
- (2023) Open ai chatgpt. [Online]. Available: https://openai.com/research/gpt-4
- Y. Fu et al., “GPT4AIGChip: Towards next-generation ai accelerator design automation via large language models,” in ICCAD, 2023, pp. 1–9.
- Z. He et al., “Chateda: A large language model powered autonomous agent for eda,” in MLCAD. IEEE, 2023, pp. 1–6.
- (2023) Anthropic. [Online]. Available: https://www.anthropic.com
- (2024) Gemini. [Online]. Available: https://deepmind.google
- T. Moreau et al., “Vta: an open hardware-software stack for deep learning,” arXiv preprint arXiv:1807.04188, vol. 10, 2018.
- R. Venkatesan et al., “Magnet: A modular accelerator generator for neural networks,” in ICCAD. IEEE, 2019, pp. 1–8.
- H. Sharma et al., “From high-level deep neural models to fpgas,” in MICRO. IEEE, 2016, pp. 1–12.
- S. Thakur et al., “Verigen: A large language model for verilog code generation,” ACM TODAES, 2023.
- K. Chang et al., “Chipgpt: How far are we from natural language hardware design,” arXiv preprint arXiv:2305.14019, 2023.
- J. Blocklove et al., “Chip-chat: Challenges and opportunities in conversational hardware design,” arXiv preprint arXiv:2305.13243, 2023.
- S. Thakur et al., “Autochip: Automating hdl generation using llm feedback,” arXiv preprint arXiv:2311.04887, 2023.
- N. Friedman, “Introducing github copilot: your ai pair programmer,” URL: https://github. blog/2021-06-29-introducing-github-copilot-ai-pair-programmer, 2021.
- H. Pearce, B. Tan, and R. Karri, “Dave: Deriving automatically verilog from english,” in Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020, pp. 27–32.
- Y. Lu et al., “Rtllm: An open-source benchmark for design rtl generation with large language model,” arXiv preprint arXiv:2308.05345, 2023.
- (2024) Scala. [Online]. Available: https://www.scala-lang.org
- J. Bachrach et al., “Chisel: constructing hardware in a scala embedded language,” in DAC, 2012, pp. 1216–1225.
- M. Chen, W. Shao, P. Xu, M. Lin, K. Zhang, F. Chao, R. Ji, Y. Qiao, and P. Luo, “Diffrate: Differentiable compression rate for efficient vision transformers,” in Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023, pp. 17 164–17 174.
- A. Amid et al., “Chipyard: Integrated design, simulation, and implementation framework for custom socs,” IEEE Micro, vol. 40, no. 4, pp. 10–21, 2020.
- Z. Wei et al., “Hlsdataset: Open-source dataset for ml-assisted fpga design using high level synthesis,” in ASAP. IEEE, 2023, pp. 197–204.
- (2023) Chat gpt-3.5. [Online]. Available: https://openai.com/blog/chatgpt
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