Papers
Topics
Authors
Recent
Assistant
AI Research Assistant
Well-researched responses based on relevant abstracts and paper content.
Custom Instructions Pro
Preferences or requirements that you'd like Emergent Mind to consider when generating responses.
Gemini 2.5 Flash
Gemini 2.5 Flash 154 tok/s
Gemini 2.5 Pro 48 tok/s Pro
GPT-5 Medium 36 tok/s Pro
GPT-5 High 33 tok/s Pro
GPT-4o 70 tok/s Pro
Kimi K2 184 tok/s Pro
GPT OSS 120B 437 tok/s Pro
Claude Sonnet 4.5 36 tok/s Pro
2000 character limit reached

Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration (2310.07424v2)

Published 11 Oct 2023 in cs.AR

Abstract: In this paper, we present a new analytical 3D placement framework with a bistratal wirelength model for F2F-bonded 3D ICs with heterogeneous technology nodes based on the electrostatic-based density model. The proposed framework, enabled GPU-acceleration, is capable of efficiently determining node partitioning and locations simultaneously, leveraging the dedicated 3D wirelength model and density model. The experimental results on ICCAD 2022 contest benchmarks demonstrate that our proposed 3D placement framework can achieve up to 6.1% wirelength improvement and 4.1% on average compared to the first-place winner with much fewer vertical interconnections and up to 9.8x runtime speedup. Notably, the proposed framework also outperforms the state-of-the-art 3D analytical placer by up to 3.3% wirelength improvement and 2.1% on average with up to 8.8x acceleration on large cases using GPUs.

Definition Search Book Streamline Icon: https://streamlinehq.com
References (48)
  1. W. Gomes, S. Morgan, B. Phelps, T. Wilson, and E. Hallnor, “Meteor lake and arrow lake intel next-gen 3d client architecture platform with foveros,” in IEEE Hot Chips 34 Symposium (HCS), 2022.
  2. B. Munger, K. Wilcox, J. Sniderman, C. Tung, B. Johnson, R. Schreiber, C. Henrion, K. Gillespie, T. Burd, H. Fair et al., ““Zen 4”: The AMD 5nm 5.7 GHz x86-64 microprocessor core,” in IEEE International Solid-State Circuits Conference (ISSCC), 2023.
  3. X. Dong, J. Zhao, and Y. Xie, “Fabrication cost analysis and cost-aware design space exploration for 3-D ICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2010.
  4. P. Batude, T. Ernst, J. Arcamone, G. Arndt, P. Coudrain, and P.-E. Gaillardon, “3-D sequential integration: A key enabling technology for heterogeneous co-integration of new function with CMOS,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2012.
  5. S. K. Samal, D. Nayak, M. Ichihashi, S. Banna, and S. K. Lim, “Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016.
  6. S. Panth, K. Samadi, Y. Du, and S. K. Lim, “Shrunk-2-D: A physical design methodology to build commercial-quality monolithic 3-D ICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.
  7. B. W. Ku, K. Chang, and S. K. Lim, “Compact-2D: A physical design methodology to build commercial-quality face-to-face-bonded 3D ICs,” in ACM International Symposium on Physical Design (ISPD), 2018.
  8. P. Morrow, C.-M. Park, S. Ramanathan, M. Kobrinsky, and M. Harmes, “Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k𝑘kitalic_k CMOS technology,” IEEE Electron Device Letters (EDL), 2006.
  9. M. Jung, T. Song, Y. Wan, Y. Peng, and S. K. Lim, “On enhancing power benefits in 3D ICs: Block folding and bonding styles perspective,” in ACM/IEEE Design Automation Conference (DAC), 2014.
  10. S. A. Panth, K. Samadi, Y. Du, and S. K. Lim, “Design and CAD methodologies for low power gate-level monolithic 3D ICs,” in IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2014.
  11. T. Song, A. Nieuwoudt, Y. S. Yu, and S. K. Lim, “Coupling capacitance in face-to-face (F2F) bonded 3D ICs: Trends and implications,” in IEEE Electronic Components and Technology Conference (ECTC), 2015.
  12. C. M. Fiduccia and R. M. Mattheyses, “A linear-time heuristic for improving network partitions,” in ACM/IEEE Design Automation Conference (DAC), 1982, pp. 175–181.
  13. J. Lu, H. Zhuang, I. Kang, P. Chen, and C.-K. Cheng, “ePlace-3D: Electrostatics based placement for 3D-ICs,” in ACM International Symposium on Physical Design (ISPD), 2016.
  14. Y.-J. Chen, Y.-S. Chen, W.-C. Tseng, C.-Y. Chiang, Y.-H. Lo, and Y.-W. Chang, “Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies,” in ACM/IEEE Design Automation Conference (DAC), 2023.
  15. K.-S. Hu, I.-J. Lin, Y.-H. Huang, H.-Y. Chi, Y.-H. Wu, and C.-F. C. Shen, “2022 ICCAD CAD Contest Problem B: 3D Placement with D2D Vertical Connections,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022.
  16. J. Cong, G. Luo, J. Wei, and Y. Zhang, “Thermal-aware 3D IC placement via transformation,” in IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2007.
  17. Y. Deng and W. P. Maly, “Interconnect characteristics of 2.5-D system integration scheme,” in ACM International Symposium on Physical Design (ISPD), 2001.
  18. S. Das, A. Chandrakasan, and R. Reif, “Design tools for 3-D integrated circuits,” in IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2003.
  19. B. Goplen and S. Spatnekar, “Placement of 3D ICs with thermal and interlayer via considerations,” in ACM/IEEE Design Automation Conference (DAC), 2007.
  20. D. H. Kim, K. Athikulwongse, and S. K. Lim, “A study of through-silicon-via impact on the 3D stacked IC layout,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2009.
  21. K. Chang, S. Sinha, B. Cline, R. Southerland, M. Doherty, G. Yeric, and S. K. Lim, “Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016.
  22. H. Park, B. W. Ku, K. Chang, D. E. Shim, and S. K. Lim, “Pseudo-3D approaches for commercial-grade RTL-to-GDS tool flow targeting monolithic 3D ICs,” in ACM International Symposium on Physical Design (ISPD), 2020.
  23. S. S. K. Pentapati, K. Chang, V. Gerousis, R. Sengupta, and S. K. Lim, “Pin-3D: A physical synthesis and post-layout optimization flow for heterogeneous monolithic 3D ICs,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020.
  24. P. Vanna-Iampikul, C. Shao, Y.-C. Lu, S. Pentapati, and S. K. Lim, “Snap-3D: A constrained placement-driven physical design methodology for face-to-face-bonded 3D ICs,” in ACM International Symposium on Physical Design (ISPD), 2021.
  25. Y.-C. Lu, S. S. K. Pentapati, L. Zhu, K. Samadi, and S. K. Lim, “TP-GNN: A graph neural network framework for tier partitioning in monolithic 3D ICs,” in ACM/IEEE Design Automation Conference (DAC), 2020.
  26. G. Murali, S. M. Shaji, A. Agnesina, G. Luo, and S. K. Lim, “ART-3D: Analytical 3D placement with reinforced parameter tuning for monolithic 3D ICs,” in ACM International Symposium on Physical Design (ISPD), 2022.
  27. I. Kaya, M. Olbrich, and E. Barke, “3-D placement considering vertical interconnects,” in IEEE International System-on-Chip Conference (SOCC), 2003.
  28. R. Hentschke, G. Flach, F. Pinto, and R. Reis, “Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing,” in Proceedings of Symposium on Integrated Circuits and Systems Design (SBCCI), 2006.
  29. T. Tanprasert, “An analytical 3-D placement that reserves routing space,” in IEEE International Symposium on Circuits and Systems (ISCAS), vol. 3, 2000.
  30. B. Goplen and S. Sapatnekar, “Efficient thermal placement of standard cells in 3D ICs using a force directed approach,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2003.
  31. M.-K. Hsu, Y.-W. Chang, and V. Balabanov, “TSV-aware analytical placement for 3D IC designs,” in ACM/IEEE Design Automation Conference (DAC), 2011.
  32. M.-K. Hsu, V. Balabanov, and Y.-W. Chang, “TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2013.
  33. A. B. Kahng and Q. Wang, “Implementation and extensibility of an analytic placer,” in ACM International Symposium on Physical Design (ISPD), 2004.
  34. G. Luo, Y. Shi, and J. Cong, “An analytical placement framework for 3-D ICs and its extension on thermal awareness,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2013.
  35. J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-H. Huang, C.-C. Teng, and C.-K. Cheng, “FFTPL: An analytic placement algorithm using fast fourier transform for density equalization,” in IEEE International Conference on ASIC (ASICON), 2013.
  36. ——, “eplace: Electrostatics-based placement using fast fourier transform and nesterov’s method,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2015.
  37. J. Lu, H. Zhuang, P. Chen, H. Chang, C.-C. Chang, Y.-C. Wong, L. Sha, D. Huang, Y. Luo, C.-C. Teng et al., “ePlace-MS: Electrostatics-based placement for mixed-size circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2015.
  38. C.-K. Cheng, A. B. Kahng, I. Kang, and L. Wang, “RePlAce: Advancing solution quality and routability validation in global placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.
  39. Y. Lin, S. Dhar, W. Li, H. Ren, B. Khailany, and D. Z. Pan, “DREAMPlace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placement,” in ACM/IEEE Design Automation Conference (DAC), 2019.
  40. L. Liu, B. Fu, M. D. Wong, and E. F. Young, “Xplace: an extremely fast and extensible global placement framework,” in ACM/IEEE Design Automation Conference (DAC), 2022.
  41. W. C. Naylor, R. Donelly, and L. Sha, “Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer,” Oct. 9 2001, US Patent 6,301,693.
  42. P. Liao, H. Liu, Y. Lin, B. Yu, and M. Wong, “On a Moreau Envelope wirelength model for analytical global placement,” in ACM/IEEE Design Automation Conference (DAC), 2023.
  43. D. Hill, “Method and system for high speed detailed placement of cells within an integrated circuit design,” Apr. 9 2002, US Patent 6,370,673.
  44. P. Spindler, U. Schlichtmann, and F. M. Johannes, “Abacus: Fast legalization of standard cell circuits with minimal movement,” in ACM International Symposium on Physical Design (ISPD), 2008.
  45. Y. Lin, W. Li, J. Gu, H. Ren, B. Khailany, and D. Z. Pan, “ABCDPlace: Accelerated batch-based concurrent detailed placement on multithreaded CPUs and GPUs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
  46. M. Pan, N. Viswanathan, and C. Chu, “An efficient and effective detailed placement algorithm,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2005.
  47. S. Popovych, H.-H. Lai, C.-M. Wang, Y.-L. Li, W.-H. Liu, and T.-C. Wang, “Density-aware detailed placement with instant legalization,” in ACM/IEEE Design Automation Conference (DAC), 2014.
  48. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2008.
Citations (2)
View on Semantic Scholar

Summary

We haven't generated a summary for this paper yet.

Ai Sparkles Streamline Icon: https://streamlinehq.com Summarize Now
Dice Question Streamline Icon: https://streamlinehq.com

Open Problems

We haven't generated a list of open problems mentioned in this paper yet.

Ai Sparkles Streamline Icon: https://streamlinehq.com Generate Now
Lightbulb Streamline Icon: https://streamlinehq.com

Continue Learning

We haven't generated follow-up questions for this paper yet.

Ai Sparkles Streamline Icon: https://streamlinehq.com Generate Now
List To Do Tasks Checklist Streamline Icon: https://streamlinehq.com

Collections

Sign up for free to add this paper to one or more collections.

User Circle Single Streamline Icon: https://streamlinehq.com Sign Up