Benchmarking a trapped-ion quantum computer with 30 qubits (2308.05071v2)

Abstract: Quantum computers are rapidly becoming more capable, with dramatic increases in both qubit count and quality. Among different hardware approaches, trapped-ion quantum processors are a leading technology for quantum computing, with established high-fidelity operations and architectures with promising scaling. Here, we demonstrate and thoroughly benchmark the IonQ Forte system: configured as a single-chain 30-qubit trapped-ion quantum computer with all-to-all operations. We assess the performance of our quantum computer operation at the component level via direct randomized benchmarking (DRB) across all 30 choose 2 = 435 gate pairs. We then show the results of application-oriented benchmarks and show that the system passes the suite of algorithmic qubit (AQ) benchmarks up to #AQ 29. Finally, we use our component-level benchmarking to build a system-level model to predict the application benchmarking data through direct simulation. While we find that the system-level model correlates with the experiment in predicting application circuit performance, we note quantitative discrepancies indicating significant out-of-model errors, leading to higher predicted performance than what is observed. This highlights that as quantum computers move toward larger and higher-quality devices, characterization becomes more challenging, suggesting future work required to push performance further.

• The paper presents a detailed performance analysis using Direct Randomized Benchmarking, reporting single-qubit and two-qubit error rates of 2.0×10⁻⁴ and 46.4×10⁻⁴ respectively over 435 qubit pairs.
• It validates system performance through application-oriented benchmarks, achieving circuit fidelities above the 1/e threshold for depths up to 841 two-qubit gates in tasks like Hamiltonian simulation and quantum Fourier transform.
• The study contrasts model predictions with experimental outcomes, uncovering discrepancies that point to unmodeled noise factors and underline challenges in scaling trapped-ion architectures.

Insights on "Benchmarking a Trapped-Ion Quantum Computer with 30 Qubits"

The academic paper titled "Benchmarking a Trapped-Ion Quantum Computer with 30 Qubits" outlines the thorough evaluation of a trapped-ion quantum processor, notably the IonQ Forte system, operating with a single-chain configuration of 30 qubits. As contemporary quantum computing systems increasingly push the boundaries of qubit count and fidelity, this paper contributes a detailed performance analysis that not only highlights the capabilities but also the challenges intrinsic to scaling up ion-trap systems.

Component and Application Benchmarking

The researchers applied both component-level and application-oriented benchmarks to gauge the trapped-ion quantum computer's performance, addressing a critical aspect of current quantum computing: the transition from analyzing isolated qubit operations to evaluating entire systems.

1. Component-Level Benchmarking: The paper employs Direct Randomized Benchmarking (DRB) to determine the error rates of single and two-qubit gate operations. Remarkably, the single-qubit gates exhibit error rates centered around $2.0 \times 10^{-4}$, whereas two-qubit gates show a median error rate of $46.4 \times 10^{-4}$. The evaluation covers all $435$ possible two-qubit interactions in the system, emphasizing the scalability issue where gate pairs calibration follows $\mathcal{O}(N^2)$. Importantly, the paper finds no correlation between ion distance and gate fidelity, dispelling concerns about long-chain degradation for the current scale.
2. Application-Oriented Benchmarking: The system's prowess is further validated using the QED-C application-oriented benchmarks, comprehensively covering algorithm types such as Hamiltonian simulation and quantum Fourier transform. The results reflect meaningful fidelity across a range of circuit sizes and structures. Notably, the system achieves the capability denoted as #AQ 29, implying a broad spectrum of quantum processes can maintain circuit fidelity above the $1/e$ threshold for execution depths up to $841$ two-qubit gates. This benchmark is dominated by application characteristics rather than qubit count, highlighting the depth limitation more than the width in practical scenarios.

Model Predictions versus Experimental Results

The research also examines the predictive power of component-level models concerning application circuit performance. Through simulations leveraging a depolarizing error model based on DRB rates, discrepancies between predicted outcome distributions and observed results on actual application circuits are observed. Although the model aligns qualitatively with experimental results, it consistently predicts higher fidelities, suggesting unmodeled error sources such as stochastic spin-phase noise or temporal noise variability.

Implications and Future Directions

The paper underscores the complexity emerging from scaling qubit systems beyond the confines of idealized, low-qubit environments, where error sources can become intertwined with system-level characteristics. The quantitative discrepancies noted between modeled and experimental fidelities imply that future work will need to refine noise models, possibly incorporating non-Markovian factors or interactions specific to trapped-ion architectures.

This research not only contributes robust performance metrics in the form of thorough benchmarking but also elucidates the nuanced challenges in characterizing and improving quantum computing systems as they grow in both size and operational complexity. As quantum technology pursues benchmark performance akin to classical computing ecosystems, such insights naturally prompt further inquiry into efficient, scalable quantum error correction and minimization strategies, both theoretically and in practice. The pursuit of improved noise calibration, reduced cross-talk, and enhanced computational efficiency continues, with trapped-ion architectures remaining a significant candidate for scaling quantum computing technology.