Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study (2111.02325v3)
Abstract: The number and diversity of consumer devices are growing rapidly, alongside their target applications' memory consumption. Unfortunately, DRAM scalability is becoming a limiting factor to the available memory capacity in consumer devices. As a potential solution, manufacturers have introduced emerging non-volatile memories (NVMs) into the market, which can be used to increase the memory capacity of consumer devices by augmenting or replacing DRAM. Since entirely replacing DRAM with NVM in consumer devices imposes large system integration and design challenges, recent works propose extending the total main memory space available to applications by using NVM as swap space for DRAM. However, no prior work analyzes the implications of enabling a real NVM-based swap space in real consumer devices. In this work, we provide the first analysis of the impact of extending the main memory space of consumer devices using off-the-shelf NVMs. We extensively examine system performance and energy consumption when the NVM device is used as swap space for DRAM main memory to effectively extend the main memory capacity. For our analyses, we equip real web-based Chromebook computers with the Intel Optane SSD, which is a state-of-the-art low-latency NVM-based SSD device. We compare the performance and energy consumption of interactive workloads running on our Chromebook with NVM-based swap space, where the Intel Optane SSD capacity is used as swap space to extend main memory capacity, against two state-of-the-art systems: (i) a baseline system with double the amount of DRAM than the system with the NVM-based swap space; and (ii) a system where the Intel Optane SSD is naively replaced with a state-of-the-art (yet slower) off-the-shelf NAND-flash-based SSD, which we use as a swap space of equivalent size as the NVM-based swap space.
- Google LLC, “Chromebook,” https://www.google.com/chromebook/.
- eMarketer, “Slowing Growth Ahead for Worldwide Internet Audience,” 2016.
- V. J. Reddi, H. Yoon, and A. Knies, “Two Billion Devices and Counting,” IEEE Micro, 2018.
- ARM and Qualcomm, “Enabling the Next Mobile Computing Revolution with Highly Integrated ARMv8-A Based SoCs,” White Paper, 2014.
- M. Halpern, Y. Zhu, and V. J. Reddi, “Mobile CPU’s Rise to Power: Quantifying the Impact of Generational Mobile CPU Design Trends on Performance, Energy, and User Satisfaction,” in HPCA, 2016.
- Canalys, “Chromebooks Lead PC Revival in Q1 2021 With 275% Growth,” https://rb.gy/jm7xu, 2021.
- B. Heater, “As Chromebook Sales Soar in Schools, Apple and Microsoft Fight Back,” TechCrunch, 2017.
- R. H. Dennard, “Field-Effect Transistor Memory,” U.S. Patent 3,387,286, 1968.
- Y. Kim and O. Mutlu, “Memory Systems,” in Computing Handbook, Third Edition: Computer Science and Software Engineering. Taylor & Francis, 2014.
- O. Mutlu, “Lecture Notes for Digital Design and Computer Architecture – Lecture 23b: Virtual Memory,” https://rb.gy/qzj7r, 2020.
- M. Badr, C. Delconte, I. Edo, R. Jagtap, M. Andreozzi, and N. E. Jerger, “Mocktails: Capturing the Memory Behaviour of Proprietary Mobile Architectures,” in ISCA, 2020.
- A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan et al., “Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” in ASPLOS, 2018.
- J. Mohan, D. Purohith, M. Halpern, V. Chidambaram, and V. J. Reddi, “Storage on Your Smartphone Uses More Energy Than You Think,” in HotStorage, 2017.
- A. Boroumand, “Practical Mechanisms for Reducing Processor-Memory Data Movement in Modern Workloads,” Ph.D. dissertation, Carnegie Mellon University, 2020.
- R. Nelson, “The Size of iPhone’s Top Apps Has Increased by 1,000% in Four Years,” https://sensortower.com/blog/ios-app-size-growth, 2017.
- N. Lebeck, A. Krishnamurthy, H. M. Levy, and I. Zhang, “End the Senseless Killing: Improving Memory Management for Mobile Operating Systems,” in USENIX ATC, 2020.
- O. Mutlu, “Memory Scaling: A Systems Architecture Perspective,” in IMW, 2013.
- O. Mutlu and L. Subramanian, “Research Problems and Opportunities in Memory Systems,” SUPERFRI, 2015.
- Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu, “Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,” in ISCA, 2014.
- O. Mutlu and J. S. Kim, “RowHammer: A Retrospective,” TCAD, 2019.
- J. S. Kim, M. Patel, A. G. Yağlıkçı, H. Hassan, R. Azizi, L. Orosa, and O. Mutlu, “Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques,” in ISCA, 2020.
- O. Mutlu, “Main Memory Scaling: Challenges and Solution Directions,” in More than Moore Technologies for Next Generation Computer Design, 2015.
- U. Kang, H.-S. Yu, C. Park, H. Zheng, J. Halbert, K. Bains, S. Jang, and J. S. Choi, “Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling,” in The Memory Forum, 2014.
- S. Hong, “Memory Technology Trend and Future Challenges,” in IEDM, 2010.
- S. Kanev, J. P. Darago, K. Hazelwood, P. Ranganathan, T. Moseley, G.-Y. Wei, and D. Brooks, “Profiling a Warehouse-Scale Computer,” in ISCA, 2015.
- O. Mutlu, “The RowHammer Problem and Other Issues We may Face as Memory Becomes Denser,” in DATE, 2017.
- S. Ghose, A. G. Yaglikçi, R. Gupta, D. Lee, K. Kudrolli, W. X. Liu, H. Hassan, K. K. Chang, N. Chatterjee, A. Agrawal et al., “What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study,” in SIGMETRICS, 2018.
- J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson, and O. Mutlu, “An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms,” in ISCA, 2013.
- P. Frigo, E. Vannacc, H. Hassan, V. Van Der Veen, O. Mutlu, C. Giuffrida, H. Bos, and K. Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh,” in SP, 2020.
- J. Liu, B. Jaiyen, R. Veras, and O. Mutlu, “RAIDR: Retention-Aware Intelligent DRAM Refresh,” in ISCA, 2012.
- M. Patel, J. S. Kim, and O. Mutlu, “The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions,” in ISCA, 2017.
- M. K. Qureshi, D. Kim, S. Khan, P. J. Nair, and O. Mutlu, “AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems,” in DSN, 2015.
- J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li, and C. J. Radens, “Challenges and Future Directions for the Scaling of Dynamic Random-Access Memory (DRAM),” IBM JRD, 2002.
- S. Khan, D. Lee, Y. Kim, A. R. Alameldeen, C. Wilkerson, and O. Mutlu, “The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study,” in SIGMETRICS, 2014.
- S. Khan, D. Lee, and O. Mutlu, “PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM,” in DSN, 2016.
- S. Khan, C. Wilkerson, Z. Wang, A. R. Alameldeen, D. Lee, and O. Mutlu, “Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content,” in MICRO, 2017.
- D. Lee, Y. Kim, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, and O. Mutlu, “Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case,” in HPCA, 2015.
- D. Lee, S. Khan, L. Subramanian, S. Ghose, R. Ausavarungnirun, G. Pekhimenko, V. Seshadri, and O. Mutlu, “Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms,” in SIGMETRICS, 2017.
- K. K. Chang, “Understanding and Improving the Latency of DRAM-Based Memory Systems,” Ph.D. dissertation, Carnegie Mellon University, 2017.
- K. K. Chang, A. G. Yağlıkçı, S. Ghose, A. Agrawal, N. Chatterjee, A. Kashyap, D. Lee, M. O’Connor, H. Hassan, and O. Mutlu, “Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms,” in SIGMETRICS, 2017.
- K. K. Chang, A. Kashyap, H. Hassan, S. Ghose, K. Hsieh, D. Lee, T. Li, G. Pekhimenko, S. Khan, and O. Mutlu, “Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization,” in SIGMETRICS, 2016.
- K. K.-W. Chang, D. Lee, Z. Chishti, A. R. Alameldeen, C. Wilkerson, Y. Kim, and O. Mutlu, “Improving DRAM Performance by Parallelizing Refreshes with Accesses,” in HPCA, 2014.
- J. Meza, Q. Wu, S. Kumar, and O. Mutlu, “Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field,” in DSN, 2015.
- H. David, C. Fallin, E. Gorbatov, U. R. Hanebutte, and O. Mutlu, “Memory Power Management via Dynamic Voltage/Frequency Scaling,” in ICAC, 2011.
- Q. Deng, D. Meisner, L. Ramos, T. F. Wenisch, and R. Bianchini, “MemScale: Active Low-Power Modes for Main Memory,” in ASPLOS, 2011.
- A. G. Yağlıkçı, H. Luo, G. F. de Oliviera, A. Olgun, M. Patel, J. Park, H. Hassan, J. S. Kim, L. Orosa, and O. Mutlu, “Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices,” in DSN, 2022.
- L. Orosa, A. G. Yaglikci, H. Luo, A. Olgun, J. Park, H. Hassan, M. Patel, J. S. Kim, and O. Mutlu, “A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses,” in MICRO, 2021.
- H. Hassan, Y. C. Tugrul, J. S. Kim, V. Van der Veen, K. Razavi, and O. Mutlu, “Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications,” in MICRO, 2021.
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” in ISCA, 2009.
- M. K. Qureshi, V. Srinivasan, and J. A. Rivers, “Scalable High Performance Main Memory System Using Phase-Change Memory Technology,” in ISCA, 2009.
- B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger, “Phase-Change Technology and the Future of Main Memory,” IEEE Micro, 2010.
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, “Phase Change Memory Architecture and the Quest for Scalability,” CACM, 2010.
- E. Kültürsay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu, “Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative,” in ISPASS, 2013.
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang, “A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology,” in ISCA, 2009.
- H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, “Phase Change Memory,” Proc. IEEE, 2010.
- J. Meza, J. Li, and O. Mutlu, “A Case for Small Row Buffers in Non-Volatile Main Memories,” in ICCD, 2012.
- J. Meza, Y. Luo, S. Khan, J. Zhao, Y. Xie, and O. Mutlu, “A Case for Efficient Hardware/Software Cooperative Management of Storage and Memory,” in WEED, 2013.
- S. Song, A. Das, O. Mutlu, and N. Kandasamy, “Improving Phase Change Memory Performance with Data Content Aware Access,” in ISMM, 2020.
- S. Song, A. Das, O. Mutlu, and N. Kandasamy, “Aging-Aware Request Scheduling for Non-Volatile Main Memory,” in ASP-DAC, 2021.
- S. Song, A. Das, O. Mutlu, and N. Kandasamy, “Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories,” TECS, 2019.
- G. Atwood, “PCM Applications and an Outlook to the Future,” in Phase Change Memory: Device Physics, Reliability and Applications. Springer International Publishing, 2017.
- S. Bock, B. Childers, R. Melhem, D. Mossé, and Y. Zhang, “Analyzing the Impact of Useless Write-Backs on the Endurance and Energy Consumption of PCM Main Memory,” in ISPASS, 2011.
- G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, “Overview of Candidate Device Technologies for Storage-Class Memory,” IBM JRD, 2008.
- Y. Du, M. Zhou, B. R. Childers, D. Mossé, and R. Melhem, “Bit Mapping for Balanced PCM Cell Programming,” in ISCA, 2013.
- A. P. Ferreira, M. Zhou, S. Bock, B. Childers, R. Melhem, and D. Mossé, “Increasing PCM Main Memory Lifetime,” in DATE, 2010.
- L. Jiang, Y. Zhang, B. R. Childers, and J. Yang, “FPB: Fine-Grained Power Budgeting to Improve Write Throughput of Multi-Level Cell Phase Change Memory,” in MICRO, 2012.
- L. Jiang, Y. Du, B. Zhao, Y. Zhang, B. R. Childers, and J. Yang, “Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory,” TACO, 2013.
- S. Kannan, M. Qureshi, A. Gavrilovska, and K. Schwan, “Energy Aware Persistence: Reducing Energy Overheads of Memory-Based Persistence in NVMs,” in PACT, 2016.
- M. K. Qureshi, “Pay-As-You-Go: Low-Overhead Hard-Error Correction for Phase Change Memories,” in MICRO, 2011.
- M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Montano, “Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing,” in HPCA, 2010.
- M. K. Qureshi, M. M. Franceschini, L. A. Lastras-Montaño, and J. P. Karidis, “Morphable Memory System: A Robust Architecture for Exploiting Multi-Level Phase Change Memories,” in ISCA, 2010.
- A. Sebastian, T. Tuma, N. Papandreou, M. Le Gallo, L. Kull, T. Parnell, and E. Eleftheriou, “Temporal Correlation Detection Using Computational Phase-Change Memory,” Nature Commun., 2017.
- R. Wang, L. Jiang, Y. Zhang, L. Wang, and J. Yang, “Exploit Imbalanced Cell Writes to Mitigate Write Disturbance in Dense Phase Change Memory,” in DAC, 2015.
- J. Yue and Y. Zhu, “Accelerating Write by Exploiting PCM Asymmetries,” in HPCA, 2013.
- M. Zhou, Y. Du, B. Childers, R. Melhem, and D. Mossé, “Writeback-Aware Partitioning and Replacement for Last-Level Caches in Phase Change Main Memory Systems,” TACO, 2012.
- M. Zhou, Y. Du, B. R. Childers, R. Melhem, and D. Mossé, “Writeback-Aware Bandwidth Partitioning for Multi-Core Systems with PCM,” in PACT, 2013.
- H. Yoon, N. Muralimanohar, J. Meza, O. Mutlu, and N. P. Jouppi, “Techniques for Data Mapping and Buffering to Exploit Asymmetry in Multi-Level Cell (Phase Change) Memory,” SAFARI Research Group, Tech. Rep. TR-SAFARI-2013-002, 2013.
- G. Dhiman, R. Z. Ayoub, and T. Rosing, “PDRAM: A Hybrid PRAM and DRAM Main Memory System,” in DAC, 2009.
- K. Wang, J. Alzate, and P. K. Amiri, “Low-Power Non-Volatile Spintronic Memory: STT-RAM and Beyond,” J. Phys. D: Appl. Phys, 2013.
- E. Chen, D. Apalkov, Z. Diao, A. Driskill-Smith, D. Druist, D. Lottis, V. Nikitin, X. Tang, S. Watts, S. Wang et al., “Advances and Future Prospects of Spin-Transfer Torque Random Access Memory,” TMAG, 2010.
- Z. Diao, Z. Li, S. Wang, Y. Ding, A. Panchula, E. Chen, L.-C. Wang, and Y. Huai, “Spin-Transfer Torque Switching in Magnetic Tunnel Junctions and Spin-Transfer Torque Random Access Memory,” Journal of Physics: Condensed Matter, 2007.
- M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto et al., “A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM,” in IEDM, 2005.
- A. Raychowdhury, D. Somasekhar, T. Karnik, and V. De, “Design Space and Scalability Exploration of 1T-1STT MTJ Memory Arrays in the Presence of Variability and Disturbances,” in IEDM, 2009.
- H. Akinaga and H. Shima, “Resistive Random Access Memory (ReRAM) Based on Metal Oxides,” Proc. IEEE, 2010.
- H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F. T. Chen, and M.-J. Tsai, “Metal–Oxide RRAM,” Proc. IEEE, 2012.
- J. J. Yang, D. B. Strukov, and D. R. Stewart, “Memristive Devices for Computing,” Nature Nanotechnology, 2013.
- M. Kund, G. Beitel, C.-U. Pinnow, T. Rohr, J. Schumann, R. Symanczyk, K. Ufert, and G. Muller, “Conductive Bridging RAM (CBRAM): An Emerging Non-Volatile Memory Technology Scalable to Sub 20nm,” in IEDM, 2005.
- D. Bondurant, “Ferroelectronic RAM Memory Family for Critical Data Storage,” Ferroelectrics, 1990.
- B. Harris and N. Altiparmak, “Ultra-Low Latency SSDs’ Impact on Overall Energy Efficiency,” in HotStorage, 2020.
- K. Wu, Z. Guo, G. Hu, K. Tu, R. Alagappan, R. Sen, K. Park, A. C. Arpaci-Dusseau, and R. H. Arpaci-Dusseau, “The Storage Hierarchy is Not a Hierarchy: Optimizing Caching on Modern Storage Devices with Orthus,” in FAST, 2021.
- C. Wang, H. Cui, T. Cao, J. Zigman, H. Volos, O. Mutlu, F. Lv, X. Feng, and G. H. Xu, “Panthera: Holistic Memory Management for Big Data Processing Over Hybrid Memories,” in PLDI, 2019.
- R. Salkhordeh, O. Mutlu, and H. Asad, “An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories,” TC, 2019.
- H. Yoon, J. Meza, R. Ausavarungnirun, R. A. Harding, and O. Mutlu, “Row Buffer Locality Aware Caching Policies for Hybrid Memories,” in ICCD, 2012.
- J. Meza, J. Chang, H. Yoon, O. Mutlu, and P. Ranganathan, “Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management,” CAL, 2012.
- Intel Corp., “Intel® Optane™ Memory H10 with Solid State Storage,” https://rb.gy/f682j.
- J. Izraelevitz, J. Yang, L. Zhang, J. Kim, X. Liu, A. Memaripour, Y. J. Soh, Z. Wang, Y. Xu, S. R. Dulloor et al., “Basic Performance Measurements of the Intel Optane DC Persistent Memory Module,” arXiv:1903.05714 [cs.AR], 2019.
- G. Psaropoulos, I. Oukid, T. Legler, N. May, and A. Ailamaki, “Bridging the Latency Gap Between NVM and DRAM for Latency-Bound Operations,” in DaMoN, 2019.
- G. Lee, S. Shin, W. Song, T. J. Ham, J. W. Lee, and J. Jeong, “Asynchronous I/O Stack: A Low-Latency Kernel I/O Stack for Ultra-Low Latency SSDs,” in USENIX ATC, 2019.
- J. Zhang, P. Li, B. Liu, T. G. Marbach, X. Liu, and G. Wang, “Performance Analysis of 3D XPoint SSDs in Virtualized and Non-Virtualized Environments,” in ICPADS, 2018.
- S. W. Chien, S. Markidis, C. P. Sishtla, L. Santos, P. Herman, S. Narasimhamurthy, and E. Laure, “Characterizing Deep-Learning I/O Workloads in TensorFlow,” in PDSW-DISCS, 2018.
- J. Yang, B. Li, and D. J. Lilja, “Exploring Performance Characteristics of the Optane 3D XPoint Storage Technology,” TOMPECS, 2020.
- F. T. Hady, A. Foong, B. Veal, and D. Williams, “Platform Storage Performance with 3D XPoint Technology,” Proc. IEEE, 2017.
- K. Wu, A. Arpaci-Dusseau, R. Arpaci-Dusseau, R. Sen, and K. Park, “Exploiting Intel Optane SSD for Microsoft SQL Server,” in DaMoN, 2019.
- S. Imamura and E. Yoshida, “Reducing CPU Power Consumption for Low-Latency SSDs,” in NVMSA, 2018.
- Amazon.com, Inc., “Intel Optane Memory Module 16GB M.2 80mm PCIe 3.0 20nm 3D XPoint MEMPEK1W016GA,” https://amzn.to/33Z6bws.
- DRAMeXchange, “World Leading DRAM and NAND Flash Market Research Firm, with More than a Decade of Most Authoritative Database,” https://www.dramexchange.com/.
- I. B. Peng, M. B. Gokhale, and E. W. Green, “System Evaluation of the Intel Optane Byte-Addressable NVM,” in MemSys, 2019.
- B. Metzler and A. Trivedi, “Prototyping Byte-Addressable NVM Access,” in OpenFabrics Developers Workshop, 2015.
- A. Hassan, H. Vandierendonck, and D. S. Nikolopoulos, “Energy-Efficient Hybrid DRAM/NVM Main Memory,” in PACT, 2015.
- H. Chauhan, I. Calciu, V. Chidambaram, E. Schkufza, O. Mutlu, and P. Subrahmanyam, “NVMOVE: Helping Programmers Move to Byte-Based Persistence,” in INFLOW, 2016.
- H. Yoon, J. Meza, N. Muralimanohar, N. P. Jouppi, and O. Mutlu, “Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories,” TACO, 2014.
- Y. Li, S. Ghose, J. Choi, J. Sun, H. Wang, and O. Mutlu, “Utility-Based Hybrid Memory Management,” in CLUSTER, 2017.
- W. Zhang, X. Zhao, S. Jiang, and H. Jiang, “ChameleonDB: A Key-Value Store for Optane Persistent Memory,” in EuroSys, 2021.
- D.-H. Bae, I. Jo, Y. A. Choi, J.-Y. Hwang, S. Cho, D.-G. Lee, and J. Jeong, “2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives,” in ISCA, 2018.
- S. Kim and J.-S. Yang, “Optimized I/O Determinism for Emerging NVM-Based NVMe SSD in an Enterprise System,” in DAC, 2018.
- Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, “Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives,” Proc. IEEE, 2017.
- Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, and O. Mutlu, “Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation,” in SIGMETRICS, 2018.
- Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, and O. Mutlu, “HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness,” in HPCA, 2018.
- Y. Cai, S. Ghose, Y. Luo, K. Mai, O. Mutlu, and E. F. Haratsch, “Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques,” in HPCA, 2017.
- Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, and O. Mutlu, “Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory,” JSAC, 2016.
- Y. Cai, Y. Luo, S. Ghose, and O. Mutlu, “Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery,” in DSN, 2015.
- O. Mutlu, “Lecture Notes for Computer Architecture – Lecture 26: Flash Memory and Solid-State Drives,” https://rb.gy/xqis8, 2020.
- Z.-L. Ke, H.-Y. Cheng, and C.-L. Yang, “LIRS: Enabling Efficient Machine Learning on NVM-Based Storage via a Lightweight Implementation of Random Shuffling,” arXiv:1810.04509 [cs.AR], 2018.
- X. Liu, Y. Pan, Y. Li, G. Wang, and X. Liu, “An NVM SSD-Optimized Query Processing Framework,” in CIKM, 2020.
- S. Han, D. Jiang, and J. Xiong, “SplitKV: Splitting IO Paths for Different Sized Key-Value Items with Advanced Storage Devices,” in HotStorage, 2020.
- A. Papagiannis, G. Xanthakis, G. Saloustros, M. Marazakis, and A. Bilas, “Optimizing Memory-Mapped I/O for Fast Storage Devices,” in USENIX ATC, 2020.
- Y. Jia and F. Chen, “From Flash to 3D XPoint: Performance Bottlenecks and Potentials in RocksDB with Storage Evolution,” in ISPASS, 2020.
- K. Wu, A. Arpaci-Dusseau, and R. Arpaci-Dusseau, “Towards an Unwritten Contract of Intel Optane SSD,” in HotStorage, 2019.
- K. Zhong, T. Wang, X. Zhu, L. Long, D. Liu, W. Liu, Z. Shao, and E. H.-M. Sha, “Building High-Performance Smartphones via Non-Volatile Memory: The Swap Approach,” in EMSOFT, 2014.
- Y. Kim, M. Imani, S. Patil, and T. S. Rosing, “CAUSE: Critical Application Usage-Aware Memory System Using Non-Volatile Memory for Mobile Devices,” in ICCAD, 2015.
- D. Liu, K. Zhong, X. Zhu, Y. Li, L. Long, and Z. Shao, “Non-Volatile Memory Based Page Swapping for Building High-Performance Mobile Devices,” TC, 2017.
- K. Zhong, D. Liu, L. Long, J. Ren, Y. Li, and E. H.-M. Sha, “Building NVRAM-Aware Swapping Through Code Migration in Mobile Devices,” TPDS, 2017.
- J. Kim and H. Bahn, “Analysis of Smartphone I/O Characteristics — Toward Efficient Swap in a Smartphone,” IEEE Access, 2019.
- X. Zhu, D. Liu, K. Zhong, J. Ren, and T. Li, “SmartSwap: High-Performance and User Experience Friendly Swapping in Mobile Systems,” in DAC, 2017.
- J. Kim and H. Bahn, “Comparison of Hybrid and Hierarchical Swap Architectures in Android by Using NVM,” JSTS, 2018.
- K. Zhong, X. Zhu, T. Wang, D. Zhang, X. Luo, D. Liu, W. Liu, and E. H.-M. Sha, “DR. Swap: Energy-Efficient Paging for Smartphones,” in ISLPED, 2014.
- S.-H. Kim, J. Jeong, and J.-S. Kim, “Application-Aware Swapping for Mobile Systems,” TECS, 2017.
- J. Kim, C. Kim, and E. Seo, “ezswap𝑒𝑧𝑠𝑤𝑎𝑝ezswapitalic_e italic_z italic_s italic_w italic_a italic_p: Enhanced Compressed Swap Scheme for Mobile Devices,” IEEE Access, 2019.
- J. Kim and H. Bahn, “Maintaining Application Context of Smartphones by Selectively Supporting Swap and Kill,” IEEE Access, 2020.
- W. Guo, K. Chen, H. Feng, Y. Wu, R. Zhang, and W. Zheng, “MARS𝑀𝐴𝑅𝑆MARSitalic_M italic_A italic_R italic_S: Mobile Application Relaunching Speed-Up through Flash-Aware Page Swapping,” IEEE Trans. Comput., 2015.
- Y. Liang, J. Li, R. Ausavarungnirun, R. Pan, L. Shi, T.-W. Kuo, and C. J. Xue, “Acclaim: Adaptive Memory Reclaim to Improve User Experience in Android Systems,” in USENIX ATC, 2020.
- Google LLC, “Chrome Browser,” https://www.google.com/chrome/.
- Chromium Project, “MemoryPressure Tast Test,” https://rb.gy/j1ft7.
- Intel Corp., “Intel Optane SSD 900P Series,” 2018.
- A. Gutierrez, R. G. Dreslinski, T. F. Wenisch, T. Mudge, A. Saidi, C. Emmons, and N. Paver, “Full-System Analysis and Characterization of Interactive Smartphone Applications,” in IISWC, 2011.
- Y. Huang, Z. Zha, M. Chen, and L. Zhang, “Moby: A Mobile Benchmark Suite for Architectural Simulators,” in ISPASS, 2014.
- D. Pandiyan, S.-Y. Lee, and C.-J. Wu, “Performance, Energy Characterizations and Architectural Implications of an Emerging Mobile Platform Benchmark Suite - MobileBench,” in IISWC, 2013.
- B. Popper, “Google Announces Over 2 Billion Monthly Active Devices on Android,” https://rb.gy/yyk1b, 2017.
- Net Applications, “Market Share Statistics for Internet Technologies,” https://www.netmarketshare.com/.
- Chromium Project, “Blink Rendering Engine,” https://rb.gy/j32v9.
- Google LLC, “Skia Graphics Library,” https://skia.org/.
- C. Reis and S. D. Gribble, “Isolating Web Programs in Modern Browser Architectures,” in EuroSys, 2009.
- A. Barth, C. Jackson, C. Reis, T. Team et al., “The Security Architecture of the Chromium Browser,” in Technical Report. Stanford University, 2008.
- HTTP Archive, http://httparchive.org/.
- D. Rientjes, “OOM Killer Rewrite; When the Kernel Runs Out of Memory,” LinuxCon Boston, 2010.
- Google LLC, “Pixel Smartphones,” https://www.google.com/pixel/.
- S. Jennings, “Transparent Memory Compression in Linux,” LinuxCon, 2013.
- E. Shiu and S. Prakash, “System Challenges and Hardware Requirements for Future Consumer Devices: From Wearable to ChromeBooks and Devices In-Between,” in VLSI Technology, 2015.
- E. Shiu and S. Lim, “Driving Innovation in Memory Architecture of Consumer Hardware with Digital Photography and Machine Intelligence Use Cases,” in IMW, 2017.
- G. Pekhimenko, V. Seshadri, Y. Kim, H. Xin, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry, “Linearly Compressed Pages: A Low-Complexity, Low-Latency Main Memory Compression Framework,” in MICRO, 2013.
- Chromium Project, “Memory Coordinator,” https://bit.ly/3lOW7w7, 2016.
- I. Grigorik, “High Performance Networking in Chrome,” The Performance of Open Source Applications: Speed, Precision, and a Bit of Serendipity, 2013.
- S. Lohr, “For Impatient Web Users, an Eye Blink Is Just Too Long to Wait,” https://rb.gy/50zon, 2012.
- P. Chi, S. Li, C. Xu, T. Zhang, J. Zhao, Y. Liu, Y. Wang, and Y. Xie, “PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory,” in ISCA, 2016.
- L. Song, Y. Zhuo, X. Qian, H. Li, and Y. Chen, “GraphR: Accelerating Graph Processing Using ReRAM,” in HPCA, 2018.
- L. Song, X. Qian, H. Li, and Y. Chen, “PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning,” in HPCA, 2017.
- P. Yao, H. Wu, B. Gao, S. B. Eryilmaz, X. Huang, W. Zhang, Q. Zhang, N. Deng, L. Shi, H.-S. P. Wong et al., “Face Classification Using Electronic Synapses,” Nature Communications, 2017.
- M. Hu, J. P. Strachan, Z. Li, E. M. Grafals, N. Davila, C. Graves, S. Lam, N. Ge, J. J. Yang, and R. S. Williams, “Dot-Product Engine for Neuromorphic Computing: Programming 1T1M Crossbar to Accelerate Matrix-Vector Multiplication,” in DAC, 2016.
- C. Gopalan, Y. Ma, T. Gallo, J. Wang, E. Runnion, J. Saenz, F. Koushan, P. Blanchard, and S. Hollmer, “Demonstration of Conductive Bridging Random Access Memory (CBRAM) in Logic CMOS Process,” Solid-State Electronics, 2011.
- D. Jana, S. Roy, R. Panja, M. Dutta, S. Z. Rahaman, R. Mahapatra, and S. Maikap, “Conductive-Bridging Random Access Memory: Challenges and Opportunity for 3D Architecture,” NRL, 2015.
- J.-H. Cha, S. Y. Yang, J. Oh, S. Choi, S. Park, B. C. Jang, W. Ahn, and S.-Y. Choi, “Conductive-Bridging Random-Access Memories for Emerging Neuromorphic Computing,” Nanoscale, 2020.
- J. F. Scott and C. A. P. De Araujo, “Ferroelectric Memories,” Science, 1989.
- J. Scott, “Applications of Modern Ferroelectrics,” Science, 2007.
- T. Mikolajick, C. Dehm, W. Hartner, I. Kasko, M. Kastner, N. Nagel, M. Moert, and C. Mazure, “FeRAM Technology for High Density Applications,” Microelectronics Reliability, 2001.
- M. Webb, “3D XPoint Status and Forecast,” in Flash Memory Summit, 2016.
- I. Cutress and B. Tallis, “Intel Launches Optane DIMMs Up to 512GB: Apache Pass Is Here!” AnandTech, 2016.
- PCI-SIG, “PCI Express Base Specification Revision 5.0, Version 1.0,” 2019.
- O. Patil, L. Ionkov, J. Lee, F. Mueller, and M. Lang, “Performance Characterization of a DRAM-NVM Hybrid Memory Architecture for HPC Applications Using Intel Optane DC Persistent Memory Modules,” in MEMSYS, 2019.
- G. Gill, R. Dathathri, L. Hoang, R. Peri, and K. Pingali, “Single Machine Graph Analytics on Massive Datasets Using Intel Optane DC Persistent Memory,” arXiv:1904.07162 [cs.AR], 2019.
- Y. Wu, K. Park, R. Sen, B. Kroth, and J. Do, “Lessons Learned from the Early Performance Evaluation of Intel Optane DC Persistent Memory in DBMS,” in DaMoN, 2020.
- M. Weiland, H. Brunst, T. Quintino, N. Johnson, O. Iffrig, S. Smart, C. Herold, A. Bonanni, A. Jackson, and M. Parsons, “An Early Evaluation of Intel’s Optane DC Persistent Memory Module and Its Impact on High-Performance Scientific Applications,” in SC, 2019.
- A. Shanbhag, N. Tatbul, D. Cohen, and S. Madden, “Large-Scale In-Memory Analytics on Intel® Optane™ DC Persistent Memory,” in DaMoN, 2020.
- V. Mironov, I. Chernykh, I. Kulikov, A. Moskovsky, E. Epifanovsky, and A. Kudryavtsev, “Performance Evaluation of the Intel Optane DC Memory With Scientific Benchmarks,” in MCHPC, 2019.
- J. Yang, J. Kim, M. Hoseinzadeh, J. Izraelevitz, and S. Swanson, “An Empirical Guide to the Behavior and Use of Scalable Persistent Memory,” in FAST, 2020.
- L. Benson, L. Papke, and T. Rabl, “PerMA-Bench: Benchmarking Persistent Memory Access,” VLDB Endow., 2022.
- L. Xiang, X. Zhao, J. Rao, S. Jiang, and H. Jiang, “Characterizing the Performance of Intel Optane Persistent Memory: A Close Look at Its On-DIMM Buffering,” in EuroSys, 2022.
- Tom’s Hardware, “Intel Optane DIMM Pricing,” https://rb.gy/873zd, 2019.
- D. Bittman, P. Alvaro, P. Mehra, D. D. Long, and E. L. Miller, “Twizzler: A Data-Centric OS for Non-Volatile Memory,” in USENIX ATC, 2020.
- Asus, Inc., “Asus Chromebox 3,” https://rb.gy/e9cnq.
- A. Wright, “Ready for a Web OS?” CACM, 2009.
- Intel Corp., “Intel® Core i3-7100U Processor,” https://rb.gy/2ifwc, 2016.
- SK Hynix Inc., “SK Hynix 4GB DDR4 HMA851S6AFR6N-UH.”
- Transcend Information, Inc., “SATA III M.2 Solid State Drive M.2 SSD 400S,” 2020.
- Intel Corp., “Intel® Optane™ Memory M10 Series,” https://rb.gy/atuol.
- Facebook, Inc., “Facebook,” https://www.facebook.com/.
- Facebook, Inc., “Instagram,” https://about.instagram.com/about-us/.
- Facebook, Inc., “WhatsApp Messenger,” https://www.whatsapp.com/.
- Telegram FZ-LLC, “Telegram Messenger,” https://telegram.org/.
- Adobe Inc., “Adobe Acrobat Reader,” https://get.adobe.com/reader/.
- Mojang Studios, “Minecraft,” https://www.minecraft.net/.
- M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, “MiBench: A Free, Commercially Representative Embedded Benchmark Suite,” in WWC, 2001.
- C. Lee, M. Potkonjak, and W. H. Mangione-Smith, “MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems,” in MICRO, 1997.
- Chromium Project, “The Chromium Project,” https://rb.gy/osxys.
- Linux Kernel Organization, Inc., “perf: Linux Profiling with Performance Counters,” https://perf.wiki.kernel.org/index.php/Main_Page.
- Google LLC, “YouTube,” https://www.youtube.com.
- Google LLC, “Google Maps,” http://maps.google.com/.
- Google LLC, “Google Sheets,” https://www.google.com/sheets/about/.
- Google LLC, “Google Docs,” https://www.google.com/docs/about/.
- Twitter, Inc., “Twitter,” https://www.twitter.com/.
- Chromium Project, “Chromium Media,” https://rb.gy/n4bnw.
- FFmpeg Team, “FFmpeg Documentation,” https://rb.gy/tr393.
- WebM Project, “WebM,” https://www.webmproject.org/code/.
- A. Grange, P. De Rivaz, and J. Hunt, “VP9 Bitstream & Decoding Process Specification,” https://rb.gy/1cfjh.
- Web Hypertext Application Technology Working Group, “HTML Living Standard,” https://html.spec.whatwg.org/multipage/, 2021.
- Chromium Project, “Mojo,” https://rb.gy/ynbj8.
- Chromium Project, “VaAPI,” https://rb.gy/5ri9b.
- Chromium Project, “SkGifCodec,” https://rb.gy/gzenm.
- Chromium Project, “V8 JavaScript Engine,” https://v8.dev/.
- Chromium Project, “Tast,” https://rb.gy/073gv.
- Google LLC, “chrome.automation,” https://rb.gy/t6kxp.
- J. Choe, “Intel 3D XPoint Memory Die Removed from Intel Optane PCM (Phase Change Memory),” TechInsights, 2017.
- J. Chen, R. C. Chiang, H. H. Huang, and G. Venkataramani, “Energy-Aware Writes to Non-Volatile Main Memory,” OSR, 2012.
- B. Zolnierkiewicz, “Efficient Memory Management on Mobile Devices,” LinuxCon, 2013.
- B. K. Tanaka, “Monitoring Virtual Memory With vmstat,” Linux Journal, 2005.
- Y. Guo, Y. Hua, and P. Zuo, “A Latency-Optimized and Energy-Efficient Write Scheme in NVM-Based Main Memory,” TCADICS, 2018.
- J.-H. Choi and G.-H. Park, “NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors,” TPDS, 2017.
- S. Swami, J. Rakshit, and K. Mohanram, “SECRET: Smartly Encrypted Energy Efficient Non-Volatile Memories,” in DAC, 2016.
- Intel Corp., “Intel® Optane™ Memory,” https://rb.gy/v31hy.
- Y.-M. Chang, P.-C. Hsiu, Y.-H. Chang, C.-H. Chen, T.-W. Kuo, and C.-Y. M. Wang, “Improving PCM Endurance with a Constant-Cost Wear Leveling Design,” TODAES, 2016.
- H. Aghaei Khouzani, Y. Xue, C. Yang, and A. Pandurangi, “Prolonging PCM Lifetime Through Energy-Efficient, Segment-Aware, and Wear-Resistant Page Allocation,” in ISLPED, 2014.
- F. T. Hady, “Intel Optane Technology Delivers New Levels of Endurance,” https://rb.gy/c83ee, (Accessed on 06/21/2023).
- M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali, “Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling,” in MICRO, 2009.
- Micron Technology, Inc., “SLC NAND,” https://rb.gy/855sx.
- J. Handy, “Examining 3D XPoint’s 1,000 Times Endurance Benefit – The Memory Guy,” https://rb.gy/mvd5a.
- diskprices.com, “Disk Prices (US),” https://bit.ly/2STO9We, accessed on April 2, 2020.
- A. C. de Melo, “The New Linux ’perf’ Tools,” in Linux Kongress, 2010.
- M. Bjørling, J. Axboe, D. Nellans, and P. Bonnet, “Linux Block IO: Introducing Multi-Queue SSD Access on Multi-Core Systems,” in SYSTOR, 2013.
- A. Tavakkol, M. Sadrosadati, S. Ghose, J. Kim, Y. Luo, Y. Wang, N. M. Ghiasi, L. Orosa, J. Gómez-Luna, and O. Mutlu, “FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives,” in ISCA, 2018.
- A. Tavakkol, J. Gómez-Luna, M. Sadrosadati, S. Ghose, and O. Mutlu, “MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices,” in FAST, 2018.
- A. D. Brunelle, “Blktrace User Guide,” 2007.
- O. Sandoval, “Kyber MQ I/O Scheduler,” https://rb.gy/6azue, 2017.
- J. Axboe, “MQ Deadline I/O Scheduler,” https://rb.gy/xxdro, 2016.
- J. C. Bennett and H. Zhang, “Hierarchical Packet Fair Queueing Algorithms,” TON, 1997.
- J. Yang, D. B. Minturn, and F. Hady, “When Poll is Better Than Interrupt,” in FAST, 2012.
- D. Le Moal, “I/O Latency Optimization with Polling,” in Vault, 2017.
- Linux Kernel Organization, Inc., “Linux Kernel Documentation: Queue sysfs Files,” https://rb.gy/9thuf, 2009.
- Intel Corp., “Tuning the Performance of Intel Optane SSDs on Linux Operating Systems,” https://rb.gy/uunhr.
- L. Yavits, L. Orosa, S. Mahar, J. D. Ferreira, M. Erez, R. Ginosar, and O. Mutlu, “WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders,” in ICCD, 2020.
- C.-H. Chen, P.-C. Hsiu, T.-W. Kuo, C.-L. Yang, and C.-Y. M. Wang, “Age-Based PCM Wear Leveling with Nearly Zero Search Cost,” in DAC, 2012.
- S.-W. Cheng, Y.-H. Chang, T.-Y. Chen, Y.-F. Chang, H.-W. Wei, and W.-K. Shih, “Efficient Warranty-Aware Wear Leveling for Embedded Systems with PCM Main Memory,” VLSI, 2016.
- J. Fan, S. Jiang, J. Shu, L. Sun, and Q. Hu, “WL-Reviver: A Framework for Reviving any Wear-Leveling Techniques in the Face of Failures on Phase Change Memory,” in DSN, 2014.
- Y. Han, J. Dong, K. Weng, Y. Wang, and X. Li, “Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation,” VLSI, 2015.
- S. Im and D. Shin, “Differentiated Space Allocation for Wear Leveling on Phase-Change Memory-Based Storage Device,” TCE, 2014.
- Y. Joo, D. Niu, X. Dong, G. Sun, N. Chang, and Y. Xie, “Energy-and Endurance-Aware Design of Phase Change Memory Caches,” in DATE, 2010.
- D. Liu, T. Wang, Y. Wang, Z. Shao, Q. Zhuge, and E. H.-M. Sha, “Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems,” TCAD, 2014.
- M. K. Qureshi, A. Seznec, L. A. Lastras, and M. M. Franceschini, “Practical and Secure PCM Systems by Online Detection of Malicious Write Streams,” in HPCA, 2011.
- G. Lee, W. Jin, W. Song, J. Gong, J. Bae, T. J. Ham, J. W. Lee, and J. Jeong, “A Case for Hardware-Based Demand Paging,” in ISCA, 2020.
- K. Oh, J. Park, and Y. I. Eom, “H-BFQ: Supporting Multi-Level Hierarchical Cgroup in BFQ Scheduler,” in BigCom, 2020.
- W. Shin, Q. Chen, M. Oh, H. Eom, and H. Y. Yeom, “OS I/O Path Optimizations for Flash Solid-State Drives,” in USENIX ATC, 2014.
- D. Vučinić, Q. Wang, C. Guyot, R. Mateescu, F. Blagojević, L. Franca-Neto, D. Le Moal, T. Bunker, J. Xu, S. Swanson et al., “DC Express: Shortest Latency Protocol for Reading Phase Change Memory Over PCI Express,” in FAST, 2014.
- J. Zhang, M. Kwon, D. Gouk, S. Koh, C. Lee, M. Alian, M. Chun, M. T. Kandemir, N. S. Kim, J. Kim et al., “FlashShare: Punching Through Server Storage Stack from Kernel to Firmware for Ultra-Low Latency SSDs,” in OSDI, 2018.
- M. Liu, H. Liu, C. Ye, X. Liao, H. Jin, Y. Zhang, R. Zheng, and L. Hu, “Towards Low-Latency I/O Services for Mixed Workloads Using Ultra-Low Latency SSDs,” in ICS, 2022.
- A. M. Caulfield, T. I. Mollov, L. A. Eisner, A. De, J. Coburn, and S. Swanson, “Providing Safe, User Space Access to Fast, Solid State Disks,” in ASPLOS, 2012.
- H.-J. Kim, Y.-S. Lee, and J.-S. Kim, “NVMeDirect: A User-Space I/O Framework for Application-Specific Optimization on NVMe SSDs,” in HotStorage, 2016.
- S. Scargall, “Introducing the Persistent Memory Development Kit,” in Programming Persistent Memory. Springer, 2020.
- Z. Yang, J. R. Harris, B. Walker, D. Verkamp, C. Liu, C. Chang, G. Cao, J. Stern, V. Verma, and L. E. Paul, “SPDK: A Development Kit to Build High Performance Storage Applications,” in CloudCom, 2017.
- Samsung Electronics Co., Ltd., “Open Memory Platform Development Kit: User Level NVMe Driver,” https://github.com/OpenMPDK/uNVMe.
- S. Peter, J. Li, I. Zhang, D. R. Ports, D. Woos, A. Krishnamurthy, T. Anderson, and T. Roscoe, “Arrakis: The Operating System Is the Control Plane,” TOCS, 2015.
- H.-J. Kim and J.-S. Kim, “A User-Space Storage I/O Framework for NVMe SSDs in Mobile Smart Devices,” TCE, 2017.
- Y. Kwon, H. Fingler, T. Hunt, S. Peter, E. Witchel, and T. Anderson, “Strata: A Cross Media File System,” in SOSP, 2017.
- K. Wu, F. Ober, S. Hamlin, and D. Li, “Early Evaluation of Intel Optane Non-Volatile Memory with HPC I/O Workloads,” arXiv:1708.02199 [cs.AR], 2017.
- Z. Lu and Q. Cao, “A Case Study of Migrating RocksDB on Intel Optane Persistent Memory,” in NAS, 2021.
- G. Singh, R. Nadig, J. Park, R. Bera, N. Hajinazar, D. Novo, J. Gómez-Luna, S. Stuijk, H. Corporaal, and O. Mutlu, “Sibyl: Adaptive and Extensible Data Placement in Hybrid Storage Systems Using Online Reinforcement Learning,” in ISCA, 2022.
- G. Oh, S. Kim, S.-W. Lee, and B. Moon, “SQLite Optimization with Phase Change Memory for Mobile Applications,” VLDB Endow., 2015.
- Y. Li, L. Zeng, G. Chen, C. Gu, F. Luo, W. Ding, Z. Shi, and J. Fuentes, “A Multi-Hashing Index for Hybrid DRAM-NVM Memory Systems,” JSA, 2022.
- A. Raybuck, T. Stamler, W. Zhang, M. Erez, and S. Peter, “HeMem: Scalable Tiered Memory Management for Big Data Applications and Real NVM,” in SOSP, 2021.
Sponsored by Paperpile, the PDF & BibTeX manager trusted by top AI labs.
Get 30 days freePaper Prompts
Sign up for free to create and run prompts on this paper using GPT-5.
Top Community Prompts
Collections
Sign up for free to add this paper to one or more collections.