Validate the Ozaki 2.5 SIMT residual instruction count

Establish the compiled SASS-level instruction count and achieved throughput of the proposed approximately 6.3-instruction-per-modulus SIMT residual for scaling and truncation, final modular reduction, limb recombination, and Karatsuba splitting.

Background

The proposed deconstruction path leaves nonlinear operations on the SIMT pipeline and estimates their cost as approximately 4/r+1+2+3≈6.34/r+1+2+3\approx6.3 instructions per modulus. The estimate is based on an instruction ledger rather than compiled code and may differ because constant division can compile into multiple multiply-high operations.

The resulting crossover and large-output floor depend materially on this count. The paper therefore identifies SASS auditing, issue-rate measurement, register and occupancy analysis, and end-to-end size sweeps as unresolved validation tasks.

References

Together with the limb recombination of O2: Eq.~eq:floor, $c_q{\text{res} \approx 6.3$---an instruction-ledger projection to be verified at SASS level (constant division compiles to multiply-high sequences, not single instructions), implemented at dp4a/narrow-integer grain (Eq.~eq:dp4a) where the ISA allows.

— Ozaki 2.5: Engineering the Deconstruction Path of fp64-Emulated Dense Matrix Multiplication on FP8 Tensor Cores  (2609.09095 - Matsuoka, 8 Sep 2026) in Section 5, paragraphs “O3: the proposed SIMT residual” and “O3$'$: closing the nonsquare S-tail layout”; Section 12, paragraph “Pass/fail criteria”

Caveats as elsewhere in this paper: greedy set selection is not proven optimal, the accuracy contract must be re-verified per set against the source analysis, the 3-pass schedule is assumed for balanced-digit Karatsuba, and $\eta_{\text{red}$, tile shape, and int8/fp#1{8} concurrency remain measurement questions; the candidate sets therefore join the validation sweep of \S~\ref{sec:validation}.

— Ozaki 2.5: Engineering the Deconstruction Path of fp64-Emulated Dense Matrix Multiplication on FP8 Tensor Cores  (2609.09095 - Matsuoka, 8 Sep 2026) in Section 6, paragraph “Regime-switched dispatch”