Support for SystemVerilog Assertions in Proprietary Formal Tools

Determine whether the stated Network-on-Chip liveness property, expressed as a SystemVerilog Assertion, is supported by various proprietary formal verification tools.

Background

The paper formulates a global liveness property for a generated Network-on-Chip, namely that every message entering the network is eventually delivered to its destination. The authors note that this property is valid according to the SystemVerilog Assertion standard, but its practical verification depends on whether commercial or proprietary formal tools implement and support the relevant assertion constructs.

This unresolved tool-support question is important because the paper argues that directly verifying instantiated Network-on-Chip designs with conventional SystemVerilog-based formal tools becomes prohibitively expensive as the network size grows. Establishing tool support would therefore be necessary to assess whether the proposed SVA formulation can be used in existing proprietary verification workflows.