Tamper-proof and privacy-preserving designs for hardware-enabled mechanisms

Develop hardware-enabled mechanisms for AI verification and enforcement—embedded in AI-capable chips and associated hardware—that provide stronger tamper-resistance and privacy-preserving guarantees, specifying concrete design approaches and threat models that achieve these properties.

Background

The paper proposes hardware-enabled mechanisms—such as on-chip reporting and tracking—to enhance verification and enforcement of international AI agreements. These mechanisms could complement inspections and national technical means by providing low-level, harder-to-bypass telemetry or controls.

However, the authors emphasize that such mechanisms must balance robustness against tampering with protections for privacy and proprietary information. They explicitly flag unresolved questions about achieving tamper-proofing and privacy simultaneously, indicating the need for technical designs and standards that address both concerns.