Compiler coordination of speculation and recovery across AGU and CU control-flow graphs in DAE

Develop a compiler transformation framework for decoupled access/execute architectures that coordinates speculative hoisting of memory requests in the address-generation unit and recovery via predicated-store poisoning in the compute unit across their distinct control-flow graphs, ensuring correct matching of FIFO-ordered store requests and corresponding store values or kill signals on all control-flow paths to preserve decoupling and program correctness.

Background

Decoupled Access/Execute (DAE) architectures separate address generation (AGU) from computation (CU) to hide memory latency via FIFO-based communication. However, when store addresses or decisions depend on loaded values, control dependencies induce a loss of decoupling, preventing the AGU from running ahead.

A natural remedy is to speculate store requests in the AGU and invalidate mis-speculations in the CU via predicated stores. The central difficulty is ensuring that the order of speculated store requests issued by the AGU exactly matches, on every path, the order of store values or kill signals produced by the CU, given that the AGU and CU have distinct control-flow graphs. Prior work only handled simple CFG shapes; a general compiler method is nontrivial.