Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (2303.08256v2)
Abstract: Reasoning high-level abstractions from bit-blasted Boolean networks (BNs) such as gate-level netlists can significantly benefit functional verification, logic minimization, datapath synthesis, malicious logic identification, etc. Mostly, conventional reasoning approaches leverage structural hashing and functional propagation, suffering from limited scalability and inefficient usage of modern computing power. In response, we propose a novel symbolic reasoning framework exploiting graph neural networks (GNNs) and GPU acceleration to reason high-level functional blocks from gate-level netlists, namely Gamora, which offers high reasoning performance w.r.t exact reasoning algorithms, strong scalability to BNs with over 33 million nodes, and generalization capability from simple to complex designs. To further demonstrate the capability of Gamora, we also evaluate its reasoning performance after various technology mapping options, since technology-dependent optimizations are known to make functional reasoning much more challenging. Experimental results show that (1) Gamora reaches almost 100% and over 97% reasoning accuracy for carry-save-array (CSA) and Booth-encoded multipliers, respectively, with up to six orders of magnitude speedups compared to the state-of-the-art implementation in the ABC framework; (2) Gamora maintains high reasoning accuracy (>92%) in finding functional modules after complex technology mapping, upon which we comprehensively analyze the impacts on Gamora reasoning from technology mapping.
- Abbas Acar et al. A survey on homomorphic encryption schemes: Theory and implementation. CSUR, 2018.
- Lilas Alrahis et al. Gnn-re: Graph neural networks for reverse engineering of gate-level netlists. IEEE TCAD, 2021.
- Ulbert J Botero et al. Hardware trust and assurance through reverse engineering: A tutorial and outlook from image analysis and machine learning perspectives. ACM JETC, 2021.
- Abc: An academic industrial-strength verification tool. In Proc. CAV. Springer, 2010.
- Tim Bucher et al. Appgnn: Approximation-aware functional reverse engineering using graph neural networks. arXiv:2208.10868, 2022.
- Reverse engineering digital ics through geometric embedding of circuit graphs. ACM TODAES, 2018.
- Maciej Ciesielski et al. Understanding algebraic rewriting for arithmetic circuit verification: a bit-flow model. IEEE TCAD, 2019.
- Fast graph representation learning with PyTorch Geometric. In ICLR Workshop on Representation Learning on Graphs and Manifolds, 2019.
- Harry Foster. The 2022 wilson research group functional verification study, Accessed: 2022.
- Adria Gascón et al. Template-based circuit understanding. In Proc. FMCAD, 2014.
- Will Hamilton et al. Inductive representation learning on large graphs. In Proc. NeurIPS, 2017.
- Zhuolun He et al. Graph learning-based arithmetic block identification. In Proc. ICCAD, 2021.
- Daniela Kaufmann et al. Verifying large multipliers by combining sat and computer algebra. In Proc. FMCAD, 2019.
- Haocheng Li et al. Attacking split manufacturing from a deep learning perspective. In Proc. DAC, 2019.
- Wenchao Li et al. Wordrev: Finding word-level structures in a sea of bit-level gates. In Proc. HOST, 2013.
- Alireza Mahzoon et al. Revsca: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers. In Proc. DAC, 2019.
- Alireza Mahzoon et al. Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. In Proc. DAC, 2022.
- Alan Mishchenko et al. Dag-aware aig rewriting: A fresh look at combinational logic synthesis. In Proc. DAC, 2006.
- Ellen M Sentovich et al. Sis: A system for sequential circuit synthesis. 1992.
- Pramod Subramanyan et al. Reverse engineering digital circuits using structural and functional analyses. IEEE TETC, 2013.
- Sound and automated verification of real-world rtl multipliers. In Proc. FMCAD, 2021.
- Vladimir Vapnik. Principles of risk minimization for learning theory. Proc. NeurIPS, 1991.
- A survey of machine learning for computer architecture and systems. ACM Comput. Surveys, 2022.
- Xiaoqing Xu et al. Standard cell library design and optimization methodology for asap7 pdk. In Proc. ICCAD, 2017.
- Cunxi Yu et al. Formal verification of arithmetic circuits by function extraction. IEEE TCAD, 2016.
- Cunxi Yu et al. Fast algebraic rewriting based on and-inverter graphs. IEEE TCAD, 2017.
- Graph neural network based netlist operator detection under circuit rewriting. In Proc. GLSVLSI, 2022.
Collections
Sign up for free to add this paper to one or more collections.
Paper Prompts
Sign up for free to create and run prompts on this paper using GPT-5.