Fully analytic valence force fields for the relaxation of group-IV semiconductor alloys: elastic properties of group-IV materials calculated from first principles (2110.11888v1)

Abstract: Si${y}$Ge${1-x-y}$(C,Sn,Pb)${x}$ alloys have attracted significant attention as a route to achieve a direct-gap group-IV semiconductor. Using density functional theory (DFT) - employing local density approximation and hybrid Heyd-Scuzeria-Ernzerhof exchange-correlation functionals - we compute the lattice parameters, relaxed and inner elastic constants, and internal strain (Kleinman) parameters for elemental (diamond) group-IV materials and zinc blende IV-IV compounds. Our DFT calculations support a little-known experimental re-evaluation of the $\alpha$-Sn elastic constants, and contradict a recent prediction of dynamic instability in selected IV-IV compounds. DFT-calculated structural and elastic properties are used in conjunction with a recently derived analytical parametrisation of a harmonic valence force field (VFF) [Phys. Rev. B 100, 094112 (2019)] to obtain a complete set of VFF potentials for Si${y}$Ge${1-x-y}$(C,Sn,Pb)${x}$ and Si${x}$Ge${1-x}$ alloys. The analytical parametrisation exactly reproduces the relaxed elastic constants and Kleinman parameter without recourse to numerical fitting, allowing for accurate and computationally inexpensive lattice relaxation. The accuracy of the VFF potentials is demonstrated via comparison to the results of DFT supercell relaxation for (i) ordered Si (Ge) alloy supercells containing a substitutional C, Ge (Si), Sn or Pb impurity, where comparison is also made to a model analytical VFF, and (ii) disordered Si${x}$Ge${1-x}$ alloy supercells. The VFF potentials we present enable accurate and computationally inexpensive relaxation of large-scale supercells representing bulk-like group-IV alloys or group-IV heterostructures, providing input to first principles or empirical electronic structure calculations, and enabling structural analysis and calculation of strain fields in heterostructures for device applications.