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Diagnosis and Repair for Synthesis from Signal Temporal Logic Specifications (1602.01883v1)

Published 4 Feb 2016 in cs.SY and cs.LO

Abstract: We address the problem of diagnosing and repairing specifications for hybrid systems formalized in signal temporal logic (STL). Our focus is on the setting of automatic synthesis of controllers in a model predictive control (MPC) framework. We build on recent approaches that reduce the controller synthesis problem to solving one or more mixed integer linear programs (MILPs), where infeasibility of a MILP usually indicates unrealizability of the controller synthesis problem. Given an infeasible STL synthesis problem, we present algorithms that provide feedback on the reasons for unrealizability, and suggestions for making it realizable. Our algorithms are sound and complete, i.e., they provide a correct diagnosis, and always terminate with a non-trivial specification that is feasible using the chosen synthesis method, when such a solution exists. We demonstrate the effectiveness of our approach on the synthesis of controllers for various cyber-physical systems, including an autonomous driving application and an aircraft electric power system.

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Authors (8)
  1. Shromona Ghosh (18 papers)
  2. Dorsa Sadigh (162 papers)
  3. Pierluigi Nuzzo (33 papers)
  4. Vasumathi Raman (6 papers)
  5. Alberto Sangiovanni-Vincentelli (37 papers)
  6. S. Shankar Sastry (77 papers)
  7. Sanjit A. Seshia (105 papers)
  8. Alexandre Donze (1 paper)
Citations (48)

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