Scalable Hardware Maturity Probe for Quantum Accelerators via Harmonic Analysis of QAOA (2509.11450v1)

Abstract: As quantum processors begin operating as tightly coupled accelerators inside high-performance computing (HPC) facilities, dependable and reproducible behavior becomes a gating requirement for scientific and industrial workloads. We present a hardware-maturity probe that quantifies a device's reliability by testing whether it can repeatedly reproduce the provably global optima of single-layer Quantum Approximate Optimization Algorithm (QAOA) circuits. Using harmonic analysis, we derive closed-form upper bounds on the number of stationary points in the p=1 QAOA cost landscape for broad classes of combinatorial-optimization problems. These bounds yield an exhaustive yet low-overhead grid-sampling scheme with analytically verifiable outcomes. The probe integrates reliability-engineering notions like run-to-failure statistics, confidence-interval estimation, and reproducibility testing into a single, application-centric benchmark. Our framework supplies a standardized dependability metric for hybrid quantum-HPC (QHPC) workflows.